生命周期: | Obsolete | 零件包装代码: | DFP |
包装说明: | DFP, FL16,.3 | 针数: | 16 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.82 | Is Samacsys: | N |
模拟集成电路 - 其他类型: | PHASE LOCKED LOOP | JESD-30 代码: | R-CDFP-F16 |
JESD-609代码: | e4 | 功能数量: | 1 |
端子数量: | 16 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 封装主体材料: | CERAMIC, METAL-SEALED COFIRED |
封装代码: | DFP | 封装等效代码: | FL16,.3 |
封装形状: | RECTANGULAR | 封装形式: | FLATPACK |
电源: | 5/15 V | 认证状态: | Not Qualified |
筛选级别: | MIL-PRF-38535 Class V | 子类别: | PLL or Frequency Synthesis Circuits |
最大供电电压 (Vsup): | 18 V | 最小供电电压 (Vsup): | 3 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | MILITARY |
端子面层: | GOLD | 端子形式: | FLAT |
端子节距: | 1.27 mm | 端子位置: | DUAL |
总剂量: | 100k Rad(Si) V | Base Number Matches: | 1 |
型号 | 品牌 | 描述 | 获取价格 | 数据表 |
5962R9666402VEX | WEDC | Phase Locked Loop, CMOS, CDIP16, CERAMIC, DIP-16 |
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5962R9666402VXC | ETC | Analog Phase-Locked Loop |
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5962R9666402VXX | WEDC | IC PHASE LOCKED LOOP, CDFP16, CERAMIC, DFP-16, PLL or Frequency Synthesis Circuit |
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5962R9666501TEC | INTERSIL | CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation |
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5962R9666501TEX | WEDC | IC TTL/CMOS TO CMOS TRANSLATOR, Level Translator |
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5962R9666501TXC | INTERSIL | CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation |
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