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5962R8969301V2A PDF预览

5962R8969301V2A

更新时间: 2024-01-16 11:21:48
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 207K
描述
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CERAMIC, LCC-20

5962R8969301V2A 技术参数

生命周期:Obsolete包装说明:QCCN, LCC20,.35SQ
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.41系列:ACT
JESD-30 代码:S-CQCC-N20JESD-609代码:e0
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:95000000 Hz
最大I(ol):0.024 A位数:4
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:5 VProp。Delay @ Nom-Sup:12.5 ns
传播延迟(tpd):12.5 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:1.905 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD总剂量:100k Rad(Si) V
触发器类型:POSITIVE EDGE宽度:8.89 mm
最小 fmax:95 MHzBase Number Matches:1

5962R8969301V2A 数据手册

 浏览型号5962R8969301V2A的Datasheet PDF文件第2页浏览型号5962R8969301V2A的Datasheet PDF文件第3页浏览型号5962R8969301V2A的Datasheet PDF文件第4页浏览型号5962R8969301V2A的Datasheet PDF文件第5页浏览型号5962R8969301V2A的Datasheet PDF文件第6页浏览型号5962R8969301V2A的Datasheet PDF文件第7页 
August 1998  
54AC175 54ACT175  
Quad D Flip-Flop  
n Buffered positive edge-triggered clock  
n Asynchronous common reset  
n True and complement output  
n Outputs source/sink 24 mA  
n ’ACT175 has TTL-compatible inputs  
n Standard Microcircuit Drawing (SMD)  
— ’AC175: 5962-89552  
General Description  
The ’AC/’ACT175 is a high-speed quad D flip-flop. The de-  
vice is useful for general flip-flop requirements where clock  
and clear inputs are common. The information on the D in-  
puts is stored during the LOW-to-HIGH clock transition. Both  
true and complemented outputs of each flip-flop are pro-  
vided. A Master Reset input resets all flip-flops, independent  
of the Clock or D inputs, when LOW.  
— ’ACT175: 5962-89693  
Features  
n Edge-triggered D-type inputs  
Logic Symbols  
Connection Diagrams  
Pin Assignment  
for DIP and Flatpak  
DS100278-1  
IEEE/IEC  
DS100278-3  
Pin Assignment for LCC  
DS100278-2  
DS100278-4  
Pin Names  
D0–D3  
CP  
Description  
Data Inputs  
Clock Pulse Input  
Master Reset Input  
True Outputs  
MR  
Q0–Q3  
Q0–Q3  
Complement Outputs  
FACT® is a registered trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100278  
www.national.com  

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