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5962F9672401VRC

更新时间： 2024-09-23 22:15:27
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英特矽尔 - INTERSIL 锁存器逻辑集成电路驱动
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4页 48K
描述
Radiation Hardened Octal Three-State Transparent Latch

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5962F9672401VRC 数据手册

 浏览型号5962F9672401VRC的Datasheet PDF文件第2页浏览型号5962F9672401VRC的Datasheet PDF文件第3页浏览型号5962F9672401VRC的Datasheet PDF文件第4页 
ACS573MS  
Radiation Hardened Octal  
Three-State Transparent Latch  
January 1996  
Features  
Pinouts  
20 LEAD CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR,  
CDIP2-T20, LEAD FINISH C  
TOP VIEW  
• Devices QML Qualified in Accordance with MIL-PRF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96724 and Intersil’s QM Plan  
• 1.25 Micron Radiation Hardened SOS CMOS  
1
2
3
4
5
6
7
8
9
VCC  
Q0  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
20  
19  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day  
(Typ)  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg  
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse  
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
• Input Logic Levels  
12  
Q7  
GND 10  
11 LE  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
20 LEAD CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR,  
CDFP4-F20, LEAD FINISH C  
TOP VIEW  
• Input Current ≤ 1µA at VOL, VOH  
• Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)  
Description  
OE  
D0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
The Intersil ACS573MS is a Radiation Hardened Octal Transparent  
Latch with an active low output enable. The outputs are transparent to  
the inputs when the latch enable (LE) is High. When the latch goes low  
the data is latched. The output enable controls the three-state outputs.  
When the output enable pins (OE) are high the output is in a high  
impedance state. The latch operation is independent of the state of  
output enable.  
D1  
D2  
D3  
D4  
D5  
D6  
The ACS573MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic family.  
D7  
Q7  
LE  
GND  
The ACS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a  
Ordering Information  
PART NUMBER  
5962F9672401VRC  
5962F9672401VXC  
ACS573D/Sample  
ACS573K/Sample  
ACS573HMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
PACKAGE  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
20 Lead SBDIP  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
20 Lead Ceramic Flatpack  
20 Lead SBDIP  
o
25 C  
Sample  
Sample  
Die  
o
25 C  
20 Lead Ceramic Flatpack  
Die  
o
25 C  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518893  
File Number 4093  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
1234

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5962F9672401VRC 替代型号

型号 品牌 替代类型 描述 数据表
CD74ACT573E TI

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