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5962F9670601VEX PDF预览

5962F9670601VEX

更新时间: 2022-12-01 19:32:18
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
4页 98K
描述
AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16

5962F9670601VEX 数据手册

 浏览型号5962F9670601VEX的Datasheet PDF文件第2页浏览型号5962F9670601VEX的Datasheet PDF文件第3页浏览型号5962F9670601VEX的Datasheet PDF文件第4页 
ACS161MS  
Radiation Hardened  
4-Bit Synchronous Counter  
January 1996  
Features  
Pinouts  
16 PIN CERAMIC DUAL-IN-LINE  
MIL-STD-1835, DESIGNATOR CDIP2-T16,  
LEAD FINISH C  
• Devices QML Qualified in Accordance with MIL-PRF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96706 and Intersil’ QM Plan  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
VCC  
TC  
MR  
CP  
P0  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day  
(Typ)  
Q0  
P1  
Q1  
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg  
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse  
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
P2  
Q2  
P3  
Q3  
TE  
PE  
SPE  
GND  
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
16 PIN CERAMIC FLATPACK  
MIL-STD-1835, DESIGNATOR CDFP4-F16,  
LEAD FINISH C  
• Input Logic Levels  
TOP VIEW  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
MR  
CP  
P0  
VCC  
TC  
• Input Current 1µA at VOL, VOH  
Q0  
• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)  
P1  
Q1  
P2  
Q2  
Description  
P3  
Q3  
The Intersil ACS161MS is a Radiation Hardened 4-Bit Binary Synchronous  
Counter. The MR is an active low master reset. SPE is an active low  
Synchronous Parallel Enable which disables counting and allows data at the  
preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is  
the terminal count or carry output. Both TE and PE must be high for counting  
to occur, but are irrelevant to loading. TE low will keep TC low.  
PE  
TE  
GND  
SPE  
The ACS161MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic family.  
The ACS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a  
Ceramic Dual-In-Line Package (D suffix).  
Ordering Information  
PART NUMBER  
5962F9670601VEC  
5962F9670601VXC  
ACS161D/Sample  
ACS161K/Sample  
ACS161HMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
MIL-PRF-38535 Class V  
MIL-PRF-38535 Class V  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
16 Lead SBDIP  
o
o
-55 C to +125 C  
16 Lead Ceramic Flatpack  
16 Lead SBDIP  
o
25 C  
o
25 C  
Sample  
16 Lead Ceramic Flatpack  
Die  
o
25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518818  
File Number 3600.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1

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