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5962F9583401QXXC PDF预览

5962F9583401QXXC

更新时间: 2022-12-13 12:59:29
品牌 Logo 应用领域
艾法斯 - AEROFLEX 接收机
页数 文件大小 规格书
11页 81K
描述
Quad Receiver

5962F9583401QXXC 数据手册

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Standard Products  
UT54LVDS032 Quad Receiver  
Data Sheet  
May 22, 2003  
FEATURES  
INTRODUCTION  
The UT54LVDS032 Quad Receiver is a quad CMOS  
differential line receiver designed for applications requiring  
ultra low power dissipation and high data rates. The device  
is designed to support data rates in excess of 155.5 Mbps  
(77.7 MHz) utilizing Low Voltage Differential Signaling  
(LVDS) technology.  
q
q
q
q
q
q
q
q
>155.5 Mbps (77.7 MHz) switching rates  
+340mV differential signaling  
5 V power supply  
TTL compatible outputs  
Ultra low power CMOS technology  
8.0ns maximum propagation delay  
3.0ns maximum differential skew  
The UT54LVDS032 accepts low voltage (340mV)  
differential input signals and translates them to 5V TTL  
output levels. The receiver supports a three-state function  
that may be used to multiplex outputs. The receiver also  
supports OPEN, shorted and terminated (100W) input fail-  
safe. Receiver output will be HIGH for all fail-safe  
conditions.  
Radiation-hardened design; total dose irradiation testing to  
MIL-STD-883 Method 1019  
- Total-dose: 300 krad(Si)and 1Mrad(Si)  
- Latchup immune (LET > 111 M eV-cm2/mg)  
The UT54LVDS032 and companion quad line driver  
UT54LVDS031 provides new alternatives to high power  
pseudo-ECL devices for high speed point-to-point interface  
applications.  
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Packaging options:  
- 16-lead flatpack (dual in-line)  
Standard Microcircuit Drawing5962-95834  
- QML Q and V compliant part  
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Compatible with IEEE 1596.3SCI LVDS  
Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard  
RIN1+  
RIN1-  
+
-
ROUT1  
R1  
RIN2+  
RIN2-  
+
ROUT2  
R2  
-
RIN3+  
RIN3-  
+
-
ROUT3  
R3  
RIN4+  
RIN4-  
+
-
ROUT4  
R4  
EN  
EN  
Figure 1. UT54LVDS032 Quad Receiver Block Diagram  

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