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5962F8957701QXC PDF预览

5962F8957701QXC

更新时间: 2024-02-04 06:28:09
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
61页 1184K
描述
BCRTM

5962F8957701QXC 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:QCCN,针数:84
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.73Is Samacsys:N
地址总线宽度:16边界扫描:NO
最大时钟频率:12 MHz通信协议:MIL STD 1553B; MIL STD 1760A
数据编码/解码方法:BIPH-LEVEL(MANCHESTER)最大数据传输速率:0.125 MBps
外部数据总线宽度:16JESD-30 代码:S-CQCC-N84
低功率模式:NO串行 I/O 数:2
端子数量:84最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
筛选级别:MIL-STD-883最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子位置:QUAD总剂量:300k Rad(Si) V
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553Base Number Matches:1

5962F8957701QXC 数据手册

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UT1553 BCRTM  
p Register-oriented architecture to enhance  
FEATURES  
programmability  
p Comprehensive MIL-STD-1553 dual-redundant Bus  
Controller (BC) and Remote Terminal (RT) and  
Monitor (M) functions  
p DMA memory interface with 64K addressability  
p Internal self-test  
p MIL-STD-1773 compatible  
p Multiple message processing capability in BC  
p TimetaggingandmessagelogginginRTandMmodes  
p Radiation-hardened option available for 84-lead  
flatpack package only  
p RemoteterminaloperationsinASD/ENASD-certified  
(SEAFAC)  
p Automatic polling and intermessage delay in  
p Availablein84-pinpingridarray, 84-leadflatpack, 84-  
BC mode  
lead leadless chip-carrier  
p Programmable interrupt scheme and internally  
p Standard Microcircuit Drawing 5962-89577 available  
generated interrupt history list  
- QML Q and V compliant  
REGISTERS  
CONTROL  
STATUS  
HIGH-PRIORITY  
STD PRIORITY LEVEL  
STD PRIORITY PULSE  
MASTER  
RESET  
CURRENT BC (or M) BLOCK/  
12MHz  
RT DESCRIPTOR SPACE  
POLLING COMPARE  
BUILT-IN-TEST WORD  
CURRENT COMMAND  
INTERRUPT  
HANDLER  
CLOCK &  
RESET  
LOGIC  
INTERRUPT LOG  
LIST POINTER  
BC PROTOCOL  
&
MESSAGE  
HANDLER  
HIGH-PRIORITY  
INTERRUPT ENABLE  
PARALLEL-  
TO-SERIAL  
CONVER-  
SION  
1553  
DUAL  
DATA  
CHANNEL  
A
HIGH-PRIORITY  
INTERRUPT STATUS  
CHANNEL  
ENCODER/  
DECODER  
MODULE  
BUS  
TRANSFER  
LOGIC  
16  
16  
STANDARD INTERRUPT  
ENABLE  
1553  
SERIAL-TO-  
PARALLEL  
CONVER-  
DATA  
CHANNEL  
B
16  
RT ADDRESS  
SION  
RT/MONITOR  
PROTOCOL &  
MESSAGE  
BUILT-IN-TEST  
START COMMAND  
16  
HANDLER  
BUILT-  
IN-  
TEST  
RESET COMMAND  
16  
RT TIMER  
RESET COMMAND  
TIMERON  
ADDRESS  
GENERATOR  
16  
TIMEOUT  
DMA/CPU  
CONTROL  
MONITOR ADDRESS  
CONTROL  
MONITOR ADDRESS  
SELECT (0-15)  
DMA ARBITRATION  
ADDRESS  
REGISTER CONTROL  
DUAL-PORT MEMORY CONTROL  
MONITOR ADDRESS  
SELECT (16-31)  
16  
16  
Figure 1. BCRTM Block Diagram  
DATA  
BCRTM-1