SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E–APRIL 2000–REVISED JULY 2009
RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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FEATURES
• Rad-Tolerant: 100-kRad (Si) TID
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Bit Counting
Normalization
23456
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SEL Immune at 89MeV-cm2/mg LET Ions
QML-V Qualified, SMD 5962-98661
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1M-Bit On-Chip SRAM
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512K-Bit Internal Program/Cache (16K
32-Bit Instructions)
Highest-Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
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512K-Bit Dual-Access Internal Data (64K
Bytes)
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7-ns Instruction Cycle Time
140-MHz Clock Rate
32-Bit External Memory Interface (EMIF)
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Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
Eight 32-Bit Instructions/Cycle
Up to One GFLOPS Performance
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Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Pin Compatible With ’C6201 Fixed-Point
DSP
Four-Channel Bootloading
Direct Memory Access (DMA) Controller With
Auxiliary Channel
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SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Operating Temperature Ranges
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16-Bit Host-Port Interface (HPI)
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–55°C to 115°C
–55°C to 125°C
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Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
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VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
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Direct Interface to T1/E1, MVIP, SCSA
Framers
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Eight Highly Independent Functional Units:
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Four ALUs (Floating and Fixed Point)
Two ALUs (Fixed Point)
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ST Bus Switching Compatible
Up to 256 Channels Each
AC97 Compatible
Two Multipliers (Floating and Fixed
Point)
Serial Peripheral Interface (SPI)
Compatible (Motorola™)
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Load-Store Architecture With 32
32-Bit General-Purpose Registers
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Two 32-Bit General-Purpose Timers
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Instruction Packing Reduces Code Size
All Instructions Conditional
Flexible Phase-Locked Loop (PLL) Clock
Generator
(1)
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Instruction Set Features
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IEEE Std 1149.1 (JTAG
)
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Hardware Support for IEEE
Single-Precision Instructions
Boundary Scan Compatible
429-Pin Ceramic Ball Grid Array (CBGA/GLP)
and Ceramic Land Grid Array (CLGA/ZMB)
Package Types
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Hardware Support for IEEE
Double-Precision Instructions
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Byte Addressable (8-/16-/32-Bit Data)
32-Bit Address Range
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0.18-µm/5-Level Metal Process
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CMOS Technology
8-Bit Overflow Protection
Saturation
3.3-V I/Os, 1.9 V Internal
(1) IEEE Std 1149.1-1990 Test Access Port and Boundary Scan
Architecture
Bit-Field Extract, Set, Clear
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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