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5962-9853001Q2A PDF预览

5962-9853001Q2A

更新时间： 2024-11-05 11:08:03
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器锁存器
页数 文件大小 规格书
7页 108K
描述
具有清零端的八路 D 型触发器 | FK | 20 | -55 to 125

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5962-9853001Q2A 数据手册

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SN54AHC273, SN74AHC273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS376E – JUNE 1997 – REVISED JANUARY 2000  
SN54AHC273 . . . J OR W PACKAGE  
SN74AHC273 . . . DB, DGV, DW, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Operating Range 2-V to 5.5-V V  
CC  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
Contain Eight Flip-Flops With Single-Rail  
Outputs  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
Direct Clear Input  
Individual Data Input to Each Flip-Flop  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
13 5D  
12 5Q  
– Pattern Generators  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
11  
GND  
CLK  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) DIPs  
SN54AHC273 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
17 7D  
4
5
6
7
8
16  
15  
14  
7Q  
6Q  
6D  
description  
These circuits are positive-edge-triggered D-type  
flip-flops with a direct clear (CLR) input.  
9 10 11 12 13  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the transition time of the positive-going pulse.  
When CLK is at either the high or low level, the  
D input has no effect at the output.  
The SN54AHC273 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHC273 is characterized for operation from –40°C to 85 °C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLK  
D
X
H
L
CLR  
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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5962-9853001Q2A 替代型号

型号 品牌 替代类型 描述 数据表
SN74AC74PWR TI

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SN74AC74PW TI

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 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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