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5962-9752901NXB

更新时间： 2024-11-26 20:37:19
品牌 Logo 应用领域
德州仪器 - TI 时钟局域网数据传输PC先进先出芯片外围集成电路
页数 文件大小 规格书
19页 293K
描述
PCILynx - PCI to 1394 3.3V Link Layer with 32-bit PCI I/F, 1K FIFOs 176-LQFP

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5962-9752901NXB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP176,1.0SQ,20针数：176
Reach Compliance Code：not_compliantHTS代码：8542.31.00.01
风险等级：5.88其他特性：ALSO REQUIRES 5V SUPPLY
地址总线宽度：32边界扫描：NO
总线兼容性：PCI最大时钟频率：50 MHz
最大数据传输速率：50 MBps外部数据总线宽度：32
JESD-30 代码：S-PQFP-G176长度：24 mm
低功率模式：NO串行 I/O 数：1
端子数量：176最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP176,1.0SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class N
座面最大高度：1.6 mm子类别：Bus Controllers
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

5962-9752901NXB 数据手册

 浏览型号5962-9752901NXB的Datasheet PDF文件第2页浏览型号5962-9752901NXB的Datasheet PDF文件第3页浏览型号5962-9752901NXB的Datasheet PDF文件第4页浏览型号5962-9752901NXB的Datasheet PDF文件第5页浏览型号5962-9752901NXB的Datasheet PDF文件第6页浏览型号5962-9752901NXB的Datasheet PDF文件第7页 
TSB12LV21A  
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE  
SLLS273 – APRIL 1997  
Supports Provisions of IEEE 1394-1995  
Provides PCI Slave Function for Read/Write  
Access of Internal Registers  
(1394) Standard for High-Performance  
†
Serial Bus  
Supports the Plug-and-Play (PnP)  
Specification  
Performs the Function of a 1394 Cycle  
Master  
Provides an 8-/16-bit Zoom Video (ZV) Port  
for the Transferring of Video Data Directly  
to an External Motion Video Memory Area  
Supports 1394 Transfer Rates of 100, 200  
and 400 Mbit/s  
Provides Three Sizes of Programmable  
FIFOs  
Operates from a 3.3-V Power Supply While  
Maintaining 5-V Tolerant Inputs  
Provides PCI Bus Master Function for  
Supporting DMA Operations  
High-Performance 176-Pin PQFP (PGF)  
Package  
Compliant With PCI Specification 2.1  
description  
The TSB12LV21A (PCILynx) provides a high-performance IEEE 1394-1995 interface with the capability to  
transfer data between the 1394 phy-link interface, the PCI bus interface, and external devices connected to the  
local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical layer device and  
is supported by the on-board link layer controller (LLC). The LLC provides the control for transmitting and  
receiving 1394 packet data between the FIFO and phy-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400  
Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access  
the physical layer control and status registers by the application software.  
An internal 1K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates  
the need for external FIFOs. Separate FIFOs can be user configured to support 1394 receive, asynchronous  
transmit, and isochronous transmit transfer operations.  
The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating as both master and  
target devices. Configuration registers can be loaded from an external serial EEPROM, allowing board and  
system designers to assign their own unique identification codes. An autoboot mode allows data-moving  
systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.  
The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the  
DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is  
connected to the local bus port. The PCLs implement an instruction set that allows linking, conditional  
branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels  
are provided to accommodate programmable data types. PCLs can be chained together to form a channel  
control program that can be developed to support each DMA channel. Data can be stored in either big endian  
or little endian format eliminating the need for the host CPU to perform byte swapping. Data can be transferred  
to either 4-byte aligned locations to provide the highest performance or to nonaligned locations to provide the  
best memory use.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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5962-9752901NXB 替代型号

型号 品牌 替代类型 描述 数据表
TSB12LV21APGF TI

功能相似

 IEEE 1394-1995 BUS TO PCI BUS INTERFACE

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