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5962-9583101QRA PDF预览

5962-9583101QRA

更新时间: 2024-11-26 05:05:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
23页 740K
描述
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

5962-9583101QRA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.39
Is Samacsys:N控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:LVT
JESD-30 代码:R-GDIP-T20长度:24.2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V最大电源电流(ICC):5 mA
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):5.4 ns
认证状态:Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:5.08 mm子类别:Bus Driver/Transceiver
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:BICMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

5962-9583101QRA 数据手册

 浏览型号5962-9583101QRA的Datasheet PDF文件第2页浏览型号5962-9583101QRA的Datasheet PDF文件第3页浏览型号5962-9583101QRA的Datasheet PDF文件第4页浏览型号5962-9583101QRA的Datasheet PDF文件第5页浏览型号5962-9583101QRA的Datasheet PDF文件第6页浏览型号5962-9583101QRA的Datasheet PDF文件第7页 
ꢉ ꢋꢉ ꢌꢅ ꢍꢎꢆ ꢏ ꢐꢆꢍꢄ ꢆ ꢑꢍꢁꢀ ꢒꢍꢑꢓ ꢁꢆ ꢔꢌꢆ ꢕꢒ ꢓ ꢄꢍꢆꢐ ꢇ ꢓ  
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003  
D
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
3.3-V V  
)
CC  
D
D
D
Support Unregulated Battery Operation  
Down to 2.7 V  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
SN74LVTH573 . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVTH573 . . . J OR W PACKAGE  
SN74LVTH573 . . . DB, DW, NS,  
OR PW PACKAGE  
SN54LVTH573 . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
20  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
3
2
1 20 19  
18  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
2Q  
3Q  
4Q  
5Q  
6Q  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
18 2Q  
17 3Q  
16 4Q  
15  
14  
13  
12  
11  
5Q  
6Q  
7Q  
8Q  
LE  
9 10 11 12 13  
10  
11  
GND  
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
T
A
PACKAGE  
TOP-SIDE MARKING  
PART NUMBER  
SN74LVTH573RGYR  
SN74LVTH573DW  
SN74LVTH573DWR  
SN74LVTH573NSR  
SN74LVTH573DBR  
SN74LVTH573PW  
SN74LVTH573PWR  
SN74LVTH573GQNR  
SN74LVTH573ZQNR  
SNJ54LVTH573J  
QFN − RGY  
SOIC − DW  
Tape and reel  
Tube  
LXH573  
LVTH573  
LVTH573  
LVTH573  
LXH573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
SSOP − DB  
−40°C to 85°C  
TSSOP − PW  
LXH573  
LXH573  
Tape and reel  
VFBGA − GQN  
VFBGA − ZQN (Pb-free)  
CDIP − J  
Tape and reel  
Tube  
Tube  
Tube  
SNJ54LVTH573J  
SNJ54LVTH573W  
SNJ54LVTH573FK  
−55°C to 125°C  
CFP − W  
SNJ54LVTH573W  
SNJ54LVTH573FK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available  
at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢏ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢮꢗ ꢄꢌ ꢒꢑ ꢯ ꢌꢉꢰꢂ ꢉꢂꢊ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢋ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢩꢤ ꢝ ꢫꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢋ ꢏ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢩꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢊ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

5962-9583101QRA 替代型号

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SNJ54LVTH573J TI

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3.3V ABT OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS
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