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5962-9561401QXA

更新时间： 2024-01-26 23:05:57
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路测试输出元件信息通信管理
页数 文件大小 规格书
42页 832K
描述
SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

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5962-9561401QXA 技术参数

生命周期：Active零件包装代码：QFP
包装说明：QFF,针数：68
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.79Is Samacsys：N
系列：ABTJESD-30 代码：S-GQFP-F68
长度：12.51 mm逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER
位数：9功能数量：2
端口数量：2端子数量：68
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：QFF
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED传播延迟（tpd）：6.4 ns
认证状态：Qualified筛选级别：MIL-PRF-38535 Class Q
座面最大高度：3.86 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：FLAT
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12.51 mm
Base Number Matches：1

5962-9561401QXA 数据手册

 浏览型号5962-9561401QXA的Datasheet PDF文件第2页浏览型号5962-9561401QXA的Datasheet PDF文件第3页浏览型号5962-9561401QXA的Datasheet PDF文件第4页浏览型号5962-9561401QXA的Datasheet PDF文件第5页浏览型号5962-9561401QXA的Datasheet PDF文件第6页浏览型号5962-9561401QXA的Datasheet PDF文件第7页 
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A  
SCAN TEST DEVICES  
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS  
SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996  
Members of the Texas Instruments  
One Boundary-Scan Cell Per I/O  
SCOPE Family of Testability Products  
Architecture Improves Scan Efficiency  
Members of the Texas Instruments  
Widebus Family  
SCOPE Instruction Set  
– IEEE Standard 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port  
and Boundary-Scan Architecture  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup Resistors  
– Even-Parity Opcodes  
Packaged in 64-Pin Plastic Thin Quad Flat  
(PM) Packages Using 0.5-mm  
Center-to-Center Spacings and 68-Pin  
Ceramic Quad Flat (HV) Packages Using  
25-mil Center-to-Center Spacings  
B-Port Outputs of ’ABTH182502A Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
SN54ABTH18502A, SN54ABTH182502A . . . HV PACKAGE  
(TOP VIEW)  
9
8
7
6 5 4 3 2 1 68 67 66 65 64 63 62 61  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
1A9  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
60 1B4  
59 1B5  
58 1B6  
57 GND  
56 1B7  
55 1B8  
54 1B9  
53  
V
CC  
52 NC  
51 2B1  
50 2B2  
49 2B3  
48 2B4  
47 GND  
46 2B5  
45 2B6  
44 2B7  
V
CC  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...42

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