ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ ꢀ
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
D
D
Processed to MIL-PRF-38535 (QML)
D
D
Two Low-Power Modes
Operating Temperature Ranges:
− Military (M) −55°C to 125°C
− Special (S) −55°C to 105°C
On-Chip Memory-Mapped Peripherals:
− One Serial Port Supporting
8-/16-/24-/32-Bit Transfers
− Two 32-Bit Timers
D
D
SMD Approval
− One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
High-Performance Floating-Point Digital
Signal Processor (DSP):
− SMJ320C31-60 (5 V)
D
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC) Technology by
Texas Instruments (TI)
33-ns Instruction Cycle Time
330 Million Operations Per Second
(MOPS), 60 Million Floating-Point
Operations Per Second (MFLOPS),
30 Million Instructions Per Second
(MIPS)
D
D
D
Two- and Three-Operand Instructions
40 / 32-Bit Floating-Point /Integer Multiplier
and Arithmetic Logic Unit (ALU)
− SMJ320C31-50 (5 V)
Parallel ALU and Multiplier Execution in a
Single Cycle
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
− SMJ320C31-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
− SMJ320LC31-40 (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
− SMQ320LC31-40 (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
D
Block-Repeat Capability
D
Zero-Overhead Loops With Single-Cycle
Branches
D
D
D
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
Bus-Control Registers Configure
Strobe-Control Wait-State Generation
D
Validated Ada Compiler
D
D
D
D
D
D
D
D
32-Bit High-Performance CPU
D
Integer, Floating-Point, and Logical
Operations
16-/32-Bit Integer and 32-/40-Bit
Floating-Point Operations
D
D
D
32-Bit Barrel Shifter
32-Bit Instruction and Data Words, 24-Bit
Addresses
One 32-Bit Data Bus (24-Bit Address)
Packaging
Two 1K Word × 32-Bit Single-Cycle
Dual-Access On-Chip RAM Blocks
− 132-Lead Ceramic Quad Flatpack With
Nonconductive Tie-Bar (HFG Suffix)
− 141-Pin Ceramic Staggered Pin
Grid- Array Package (GFA Suffix)
− 132-Lead TAB Frame
Boot-Program Loader
64-Word × 32-Bit Instruction Cache
Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
− 132-Lead Plastic Quad Flatpack
(PQ Suffix)
description
The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point
processors manufactured in 0.6-µm triple-level-metal CMOS technology. The devices are part of the
SMJ320C3x generation of DSPs from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
ꢑ
ꢑ
ꢒ
ꢓ
ꢥ
ꢋ
ꢠ
ꢜ
ꢕ
ꢆ
ꢞ
ꢎ
ꢟ
ꢩ
ꢌ
ꢙ
ꢓ
ꢗ
ꢚ
ꢐ
ꢘ
ꢋ
ꢏ
ꢎ
ꢏ
ꢖ
ꢗ
ꢡ
ꢠ
ꢘ
ꢙ
ꢟ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢗ
ꢝ
ꢝ
ꢖ
ꢖ
ꢢ
ꢙ
ꢙ
ꢚ
ꢗ
ꢗ
ꢙ
ꢖ
ꢞ
ꢞ
ꢢ
ꢞ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢞ
ꢗ
ꢙ
ꢘ
ꢢ
ꢠ
ꢣ
ꢞ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢪ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢥ
ꢝ
ꢝ
ꢡ
ꢞ
ꢡ
ꢦ
Copyright 2006, Texas Instruments Incorporated
ꢓ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢁꢌ ꢉꢬ ꢑꢒ ꢭ ꢬꢃꢮꢯ ꢃꢯꢈ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢎ
ꢡ
ꢨ
ꢜ
ꢌ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢚ
ꢥ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢑ
ꢚ
ꢙ
ꢥ
ꢝ
ꢖ
ꢙ
ꢟ
ꢡ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢓ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢈ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ
ꢝ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
ꢝ
ꢡ
ꢞ
ꢖ
ꢗ
ꢫ
ꢙ
ꢘ
ꢜ
ꢤ
ꢤ
ꢢ
ꢜ
ꢚ
ꢜ
ꢛ
ꢡ
ꢝ
ꢡ
ꢚ
ꢞ
ꢦ
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
5秒后页面跳转
解析光耦仿真器：升级光耦合器技术的必要性
英伟达新一代Blackwell GPU过热问题致交付延迟
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
