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5962-9162701MCA PDF预览

5962-9162701MCA

更新时间: 2024-01-01 11:58:05
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德州仪器 - TI 栅极
页数 文件大小 规格书
5页 83K
描述
军用 4 通道、2 输入、4.5V 至 5.5V 双极与非门 | J | 14 | -55 to 125

5962-9162701MCA 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, CERAMIC, DIP-14针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
其他特性:IOH = 40MA @ VOH = 2V; IOL = 40MA @ VOL = 0.5V系列:AS
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.04 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):19 mA
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

5962-9162701MCA 数据手册

 浏览型号5962-9162701MCA的Datasheet PDF文件第2页浏览型号5962-9162701MCA的Datasheet PDF文件第3页浏览型号5962-9162701MCA的Datasheet PDF文件第4页浏览型号5962-9162701MCA的Datasheet PDF文件第5页 
SN54AS1000A, SN74AS1000A  
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS  
SDAS056B – APRIL 1984 – REVISED JANUARY 1995  
SN54AS1000A . . . J PACKAGE  
SN74AS1000A . . . D OR N PACKAGE  
(TOP VIEW)  
Driver Version of AS00  
High Capacitive-Drive Capability  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
2Y  
GND  
These devices contain four independent 2-input  
positive-NAND buffers/drivers. They perform the  
Boolean functions Y = A B or Y = A + B in positive  
logic.  
8
SN54AS1000A . . . FK PACKAGE  
(TOP VIEW)  
The SN54AS1000A is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74AS1000A is characterized for  
operation from 0°C to 70°C.  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
NC  
2B  
Y
A
H
L
B
H
X
L
9 10 11 12 13  
L
H
H
X
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1A  
2
1
&
3
6
1A  
2
3
6
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
4
1B  
4
2A  
5
2A  
5
2B  
9
2B  
3A  
10  
3B  
12  
4A  
13  
4B  
9
3A  
8
8
10  
3B  
11  
12  
4A  
11  
13  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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