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5962-9052604Q9X PDF预览

5962-9052604Q9X

更新时间： 2024-11-20 13:04:43
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
47页 721K
描述
32-BIT, 40MHz, OTHER DSP, UUC, DIE

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5962-9052604Q9X 技术参数

生命周期：Obsolete零件包装代码：DIE
包装说明：DIE,Reach Compliance Code：compliant
ECCN代码：3A001.A.2.CHTS代码：8542.31.00.01
风险等级：5.82Is Samacsys：N
地址总线宽度：24桶式移位器：YES
边界扫描：NO最大时钟频率：40 MHz
外部数据总线宽度：32格式：FLOATING POINT
内部总线架构：MULTIPLEJESD-30 代码：X-XUUC-N
低功率模式：NO最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：UNSPECIFIED
封装形式：UNCASED CHIP认证状态：Not Qualified
筛选级别：MIL-PRF-38535 Class Q最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子位置：UPPERuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

5962-9052604Q9X 数据手册

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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ  
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004  
D
−55°C to 125°C Operating Temperature  
D
D
D
Two 32-Bit External Ports  
(24- and 13-Bit Address)  
Range, QML Processing  
D
Processed to MIL-PRF-38535 (QML)  
Two Serial Ports With Support for  
8- / 16- /24- /32-Bit Transfers  
D
Performance  
− SMJ320C30-40 (50-ns Cycle)  
40 MFLOPS  
Packaging  
− 181-Pin Grid Array Ceramic Package  
(GB Suffix)  
20 MIPS  
− SMJ320C30-50 (40-ns Cycle)  
50 MFLOPS  
− 196-Pin Ceramic Quad Flatpack With  
Nonconductive Tie-Bar (HFG Suffix)  
25 MIPS  
D
D
SMD Approval for 40- and 50-MHz Versions  
D
Two 1K-Word × 32-Bit Single-Cycle  
Dual-Access On-Chip RAM Blocks  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
D
D
D
D
D
Validated Ada Compiler  
64-Word × 32-Bit Instruction Cache  
32-Bit Instruction and Data Words,  
24-Bit Addresses  
D
D
Zero-Overhead Loops With Single-Cycle  
Branches  
Interlocked Instructions for  
Multiprocessing Support  
40 / 32-Bit Floating-Point /Integer Multiplier  
and Arithmetic Logic Unit (ALU)  
D
32-Bit Barrel Shifter  
Parallel ALU and Multiplier Execution in a  
Single Cycle  
D
Eight Extended-Precision Registers  
(Accumulators)  
On-Chip Direct Memory Access (DMA)  
Controller for Concurrent I/O and CPU  
Operation  
D
D
D
D
Two- and Three-Operand Instructions  
Conditional Calls and Returns  
Block Repeat Capability  
D
D
Integer, Floating-Point, and Logical  
Operations  
Fabricated Using Enhanced Performance  
Implanted CMOS (EPICt) by Texas  
Instruments  
One 4K-Word × 32-Bit Single-Cycle  
Dual-Access On-Chip ROM Block  
D
Two 32-Bit Timers  
description  
The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and  
flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions  
in hardware that other processors implement through software or microcode. This hardware-intensive approach  
provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted  
in a less expensive processor that can be designed into systems currently using costly bit-slice processors.  
D
D
SMJ320C30-40: 50-ns single-cycle execution time, 5% supply  
SMJ320C30-50: 40-ns single-cycle execution time, 5% supply  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...47

中文翻译

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