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5962-9051601MSA

更新时间： 2024-02-11 02:15:02
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
15页 501K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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5962-9051601MSA 技术参数

生命周期：Active零件包装代码：DFP
包装说明：DFP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.73系列：BCT/FBT
JESD-30 代码：R-XDFP-F20逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：UNSPECIFIED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：11.6 ns认证状态：Qualified
筛选级别：MIL-STD-883最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子位置：DUALBase Number Matches：1

5962-9051601MSA 数据手册

 浏览型号5962-9051601MSA的Datasheet PDF文件第2页浏览型号5962-9051601MSA的Datasheet PDF文件第3页浏览型号5962-9051601MSA的Datasheet PDF文件第4页浏览型号5962-9051601MSA的Datasheet PDF文件第5页浏览型号5962-9051601MSA的Datasheet PDF文件第6页浏览型号5962-9051601MSA的Datasheet PDF文件第7页 
SN54BCT374, SN74BCT374  
OCTAL EDGE-TRIGGERED D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
State-of-the-Art BiCMOS Design  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
Significantly Reduces I  
ESD Protection Exceeds JESD 22  
CCZ  
– 2000-V Human-Body Model (A114-A)  
Full Parallel Access for Loading  
Buffered Control Inputs  
SN54BCT374 . . . J OR W PACKAGE  
SN74BCT374 . . . DW, N, OR NS PACKAGE  
(TOP VIEW)  
SN54BCT374 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
GND  
description/ordering information  
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
The eight flip-flops of the ’BCT374 devices are edge-triggered D-type flip-flops. On the positive transition of the  
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without  
need for interface or pullup components. The output-enable (OE) input does not affect internal operations of  
the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance  
state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74BCT374N  
SN74BCT374N  
Tube  
SN74BCT374DW  
SN74BCT374DWR  
SN74BCT374NSR  
SNJ54BCT374J  
SNJ54BCT374W  
SNJ54BCT374FK  
0°C to 70°C  
SOIC – DW  
BCT374  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
CDIP – J  
BCT374  
SNJ54BCT374J  
SNJ54BCT374W  
SNJ54BCT374FK  
–55°C to 125°C  
CFP – W  
LCCC – FK  
Tube  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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