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5962-8971101LA PDF预览

5962-8971101LA

更新时间: 2024-11-20 06:45:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
16页 107K
描述
Correlator, 1-Bit, CMOS, CDIP24, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-24

5962-8971101LA 数据手册

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www.fairchildsemi.com  
TMC2 0 2 3  
CMOS Dig it a l Ou t p u t Co rre la t o r  
6 4 -Bit , 2 5 , 3 0 , 3 5 , a n d 5 0 MHz  
Description  
Features  
The TMC2023 is a monolithic 64-bit correlator with a 7-bit  
three-state buffered digital output. This device consists of  
three 64-bit independently clocked shift registers, one 64-bit  
reference holding latch, and a 64-bit independently clocked  
digital summing network. The device is available in versions  
capable of 25, 30, 35, and 50 MHz parallel correlation rates.  
• 25, 30, 35, and 50 MHz correlation rates  
• All inputs and outputs TTL compatible  
• Serial data input, parallel correlation output  
• Programmable word length  
• Independently clocked registers  
• Programmable threshold detection and flag output  
• Available in 24 pin Ceramic and Plastic DIP, 28-lead  
Plastic and Ceramic chip carrier and 28-contact chip  
carrier  
The 7-bit threshold register allows the user to preload a  
binary number from 0 to 64. Whenever the correlation is  
equal to or greater than the number in the threshold register,  
the threshold flag goes HIGH.  
• Available to Standard Military Drawing (SMD)  
• Pin-Compatible with TDC1023  
• Output format flexibility  
The 64-bit shift mask register (M register) allows the user to  
mask or selectively to choose “no compare” bit positions,  
thereby accomodating any desired word length.  
• Three-state outputs  
• Low-power CMOS  
Applications  
• Check sorting equipment  
• High density recording  
• Bar code identification  
The reference word is serially shifted into the B register.  
Bringing LDR HIGH parallel loads the data into the R refer-  
ence latch. This allows the user to serially preload a new ref-  
erence word into the B register while correlation is taking  
Block Diagram  
CLK S  
INV  
A
IN  
A
A
A
A
OUT  
1
2
64  
CLK A  
PIPELINED  
DIGITAL  
SUMMER  
(3 STAGES)  
7
1
LATCH  
TFLG  
7
TS  
R
R
R
64  
T REG  
LDR  
1
2
7
CLK T  
CLK B  
B
B
B
B
OUT  
1
2
64  
B
IN  
IN  
M
M
M
M
M
OUT  
1
2
64  
CLK M  
65-2023-01  
IO  
0-6  
Rev. 1.0.0  

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