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5962-8872801RA PDF预览

5962-8872801RA

更新时间: 2024-11-08 11:06:27
品牌 Logo 应用领域
德州仪器 - TI 驱动逻辑集成电路触发器总线驱动器总线收发器
页数 文件大小 规格书
5页 85K
描述
具有三态输出的八路边沿触发式 D 型触发器 | J | 20 | -55 to 125

5962-8872801RA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.47
控制类型:INDEPENDENT CONTROL计数方向:UNIDIRECTIONAL
系列:ALSJESD-30 代码:R-GDIP-T20
长度:24.2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):30 mAProp。Delay @ Nom-Sup:24 ns
传播延迟(tpd):24 ns认证状态:Qualified
筛选级别:MIL-STD-883座面最大高度:5.08 mm
子类别:Bus Driver/Transceiver最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
触发器类型:POSITIVE EDGE宽度:6.92 mm
Base Number Matches:1

5962-8872801RA 数据手册

 浏览型号5962-8872801RA的Datasheet PDF文件第2页浏览型号5962-8872801RA的Datasheet PDF文件第3页浏览型号5962-8872801RA的Datasheet PDF文件第4页浏览型号5962-8872801RA的Datasheet PDF文件第5页 
SN54ALS564B, SN74ALS564B  
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SDAS164B – APRIL 1982 – REVISED JANUARY 1995  
SN54ALS564B . . . J OR W PACKAGE  
SN74ALS564B . . . DW OR N PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Inverting Outputs Drive  
Bus Lines Directly  
Bus-Structured Pinout  
Buffered Control Inputs  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs, and Ceramic Flat  
(W) Packages  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
description  
13 7Q  
12 8Q  
These octal D-type edge-triggered flip-flops  
feature inverting 3-state outputs designed  
specifically for bus driving. They are particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
11  
GND  
CLK  
SN54ALS564B . . . FK PACKAGE  
(TOP VIEW)  
The eight flip-flops enter data on the low-to-high  
transition of the clock (CLK) input.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
The output-enable (OE) input does not affect  
internal operations of the flip-flops. Old data can  
be retained or new data can be entered while the  
outputs are in the high-impedance state.  
17  
16  
15  
14  
9 10 11 12 13  
The SN54ALS564B is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS564B is characterized for  
operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
L
L
H
L
L
X
X
X
Q
0
H
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

5962-8872801RA 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54ALS564BJ TI

完全替代

具有三态输出的八路边沿触发式 D 型触发器 | J | 20 | -55 to 125

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QUADRUPLE 2-INPUT POSITIVE-OR BUFFERS/DRIVERS