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5962-8868701LA PDF预览

5962-8868701LA

更新时间： 2024-01-09 10:35:33
品牌 Logo 应用领域
德州仪器 - TI 驱动总线驱动器总线收发器
页数 文件大小 规格书
22页 332K
描述
具有三态输出的八路总线收发器和寄存器 | JT | 24 | -55 to 125

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5962-8868701LA 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCN,针数：28
Reach Compliance Code：unknown风险等级：5.72
其他特性：SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA系列：AS
JESD-30 代码：S-CQCC-N28长度：11.43 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：28
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
最大电源电流（ICC）：211 mA传播延迟（tpd）：11 ns
认证状态：Not Qualified座面最大高度：2.03 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD宽度：11.43 mm
Base Number Matches：1

5962-8868701LA 数据手册

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SN54ALS652, SN54ALS653, SN54AS651, SN54AS652  
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652  
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS  
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996  
SN54ALS’, SN54AS’ . . . JT PACKAGE  
SN74ALS’, SN74AS’ . . . DW OR NT PACKAGE  
Bus Transceivers/Registers  
Independent Registers and Enables for A  
(TOP VIEW)  
and B Buses  
CLKAB  
SAB  
OEAB  
A1  
V
CC  
Multiplexed Real-Time and Stored Data  
Choice of True or Inverting Data Paths  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
CLKBA  
SBA  
OEBA  
B1  
2
3
Choice of 3-State or Open-Collector  
Outputs to A Bus  
4
A2  
5
Package Options Include Plastic  
A3  
B2  
6
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
A4  
B3  
7
A5  
B4  
8
A6  
B5  
9
A7  
B6  
10  
11  
DEVICE  
A OUTPUT  
B OUTPUT  
LOGIC  
A8  
B7  
SN74ALS651A,  
’AS651  
GND 12  
13 B8  
3 State  
3 State  
Inverting  
SN54ALS652,  
SN74ALS652A,  
’AS652  
SN54ALS’, SN54AS’ . . . FK PACKAGE  
3 State  
3 State  
True  
(TOP VIEW)  
’ALS653  
Open Collector  
Open Collector  
3 State  
3 State  
Inverting  
True  
SN74ALS654  
description  
4
3
2 1 28 27 26  
5
6
7
8
9
25 OEBA  
A1  
A2  
A3  
NC  
A4  
A5  
A6  
These devices consist of bus-transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
data bus or from the internal storage registers.  
Output-enable (OEAB and OEBA) inputs are  
provided to control the transceiver functions.  
Select-control (SAB and SBA) inputs are provided  
to select real-time or stored data transfer. The  
circuitry used for select control eliminates the  
typical decoding glitch that occurs in a multiplexer  
during the transition between stored and real-time  
data. A low input level selects real-time data, and  
a high input level selects stored data. Figure 1  
24  
23  
22  
21  
20  
19  
B1  
B2  
NC  
B3  
B4  
B5  
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
illustrates the four fundamental bus-management functions that can be performed with the octal bus  
transceivers and registers.  
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at  
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When  
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type  
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.  
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains  
at its last state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...22

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