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5962-8862401JB PDF预览

5962-8862401JB

更新时间: 2024-01-29 04:47:43
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器
页数 文件大小 规格书
7页 113K
描述
HCT SERIES, ASYN POSITIVE EDGE TRIGGERED 16-BIT DOWN DIVIDE BYN COUNTER, DIP24, 1.290 X 0.610 INCH, 0.225 INCH HEIGHT, DIP-24

5962-8862401JB 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84计数方向:DOWN
系列:HCTJESD-30 代码:R-XDIP-T24
JESD-609代码:e0负载/预设输入:YES
逻辑集成电路类型:DIVIDE BY N COUNTER工作模式:ASYNCHRONOUS
位数:16功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:UNSPECIFIED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):69 ns
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子位置:DUAL
触发器类型:POSITIVE EDGE最小 fmax:25 MHz
Base Number Matches:1

5962-8862401JB 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ ꢇꢆ ꢈꢉ ꢊ  
ꢊ ꢃ ꢈꢀꢋꢌꢍ ꢎ ꢌꢀꢏ ꢁꢅꢄꢐ ꢑꢁ ꢑꢒꢀ ꢓꢔ ꢁꢌꢐꢏ ꢅꢑ ꢒꢁꢋ ꢎꢐ ꢌꢁꢕ ꢑ ꢀꢅꢔ ꢖꢖ ꢌꢋꢑ ꢐ  
SCLS599 − NOVEMBER 2004  
D OR PW PACKAGE  
(TOP VIEW)  
D
Qualification in Accordance With  
AEC-Q100  
D
Qualified for Automotive Applications  
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
L
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
Q
Q
Q
Q
M
J
H
I
Q
N
Q
Q
F
12 CLR  
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive up to Ten LSTTL Loads  
E
11  
10  
9
Q
CLKI  
G
Q
CLKO  
CLKO  
D
Low Power Consumption, 80-µA Max I  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
CC  
GND  
Low Input Current of 1 µA Max  
Allow Design of Either RC- or  
Crystal-Oscillator Circuits  
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
The SN74HC4060 device consists of an oscillator section and 14 ripple-carry binary counter stages. The  
oscillator configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the  
clock (CLKI) input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO  
goes high and CLKO goes low) and resets the counter to zero (all Q outputs low).  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Reel of 2500  
Reel of 2000  
SN74HC4060QDRQ1  
SN74HC4060QPWRQ1  
HC4060Q  
HC4060Q  
−40°C to 125°C  
TSSOP − PW  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
FUNCTION  
CLK  
CLR  
L
No change  
Advance to next stage  
All outputs L  
L
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢋꢣ  
Copyright 2004, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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