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5962-8761001CA PDF预览

5962-8761001CA

更新时间: 2024-11-21 11:06:35
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器栅极
页数 文件大小 规格书
5页 84K
描述
军用 3 通道、3 输入、2V 至 6V 与非门 | J | 14 | -55 to 125

5962-8761001CA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:1.27
系列:ACJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.024 A
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):11 ns
认证状态:Qualified施密特触发器:NO
筛选级别:MIL-STD-883座面最大高度:5.08 mm
子类别:Gate最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.67 mm
Base Number Matches:1

5962-8761001CA 数据手册

 浏览型号5962-8761001CA的Datasheet PDF文件第2页浏览型号5962-8761001CA的Datasheet PDF文件第3页浏览型号5962-8761001CA的Datasheet PDF文件第4页浏览型号5962-8761001CA的Datasheet PDF文件第5页 
SN54AC10, SN74AC10  
TRIPLE 3-INPUT POSITIVE-NAND GATES  
SCAS529B – AUGUST 1995 – REVISED SEPTEMBER 1996  
SN54AC10 . . . J OR W PACKAGE  
SN74AC10 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPS  
1A  
1B  
2A  
2B  
2C  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1Y  
3A  
3B  
3C  
3Y  
2Y  
GND  
description  
8
The ’AC10 contain three independent 3-input  
NAND gates. The devices perform the Boolean  
function Y = A B C or Y = A + B + C in positive  
logic.  
SN54AC10 . . . FK PACKAGE  
(TOP VIEW)  
The SN54AC10 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74AC10 is characterized for  
operation from 40°C to 85°C.  
3
2
1
20 19  
18  
1Y  
NC  
3A  
NC  
3B  
2A  
NC  
2B  
4
5
6
7
8
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
NC  
2C  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
C
H
X
X
L
9 10 11 12 13  
L
H
H
H
X
X
NC – No internal connection  
X
logic symbol  
logic diagram, each gate (positive logic)  
1
1A  
1
1A  
&
12  
2
12  
6
1Y  
1B  
1C  
2
1Y  
2Y  
3Y  
13  
1B  
13  
1C  
3
4
5
2A  
2B  
2C  
3
6
2A  
4
2Y  
3Y  
2B  
5
11  
10  
9
2C  
3A  
3B  
3C  
8
8
11  
3A  
10  
3B  
9
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, DB, J, N, PW, and W packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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