Datasheet > 5962-8755601VRA

5962-8755601VRA

更新时间： 2024-09-25 11:13:35

品牌	Logo	应用领域
德州仪器 - TI		驱动逻辑集成电路锁存器
页数	文件大小	规格书
27页	1601K
描述
具有三态输出的八路 D 类透明锁存器 \| J \| 20 \| -55 to 125

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5962-8755601VRA 数据手册

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544E – OCTOBER 1995 – REVISED OCTOBER 2002

SN54ACT373 . . . J OR W PACKAGE

SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

4.5-V to 5.5-V V

Operation

Inputs Accept Voltages to 5.5 V

Max t of 10 ns at 5 V

Inputs Are TTL-Voltage Compatible

description/ordering information

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

GND

The eight latches are D-type transparent latches.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

SN54ACT373 . . . FK PACKAGE

(TOP VIEW)

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in bus-organized systems without need for

interface or pullup components.

20 19

9 10 11 12 13

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP – N

Tube

SN74ACT373N

Tube

SN74ACT373DW

SN74ACT373DWR

SN74ACT373NSR

SN74ACT373DBR

SN74ACT373PWR

SNJ54ACT373J

SOIC – DW

ACT373

Tape and reel

Tube

–40°C to 85°C

SOP – NS

SSOP – DB

TSSOP – PW

CDIP – J

ACT373

AD373

SNJ54ACT373J

SNJ54ACT373W

SNJ54ACT373FK

–55°C to 125°C

CFP – W

Tube

SNJ54ACT373W

SNJ54ACT373FK

LCCC – FK

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...27

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5962-8755601VRA 替代型号

型号	品牌	替代类型	描述	数据表
5962-8755601RA	TI	完全替代	具有三态输出的八路 D 类透明锁存器 \| J \| 20 \| -55 to 125
SN74ACT373N	TI	类似代替	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

与5962-8755601VRA相关器件

型号	品牌	获取价格	描述	数据表
5962-87556023X	ETC	获取价格	8-Bit D-Type Latch
5962-8755602LX	ETC	获取价格	8-Bit D-Type Latch
5962-87557012A	ETC	获取价格	NOR and OR/NOR Gate
5962-8755701EA	ETC	获取价格	NOR and OR/NOR Gate
5962-8755701FA	ETC	获取价格	NOR and OR/NOR Gate
5962-8755701XA	ETC	获取价格	NOR and OR/NOR Gate
5962-87558012A	ETC	获取价格	Quad 2-input Exclusive OR (XOR) Gate
5962-87558012C	ETC	获取价格	Quad 2-input Exclusive OR (XOR) Gate
5962-87558012X	ETC	获取价格	Quad 2-input Exclusive OR (XOR) Gate
5962-8755801EA	ETC	获取价格	Quad 2-input Exclusive OR (XOR) Gate

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