7130SA/LA
7140SA/LA
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
◆
◆
On-chip port arbitration logic (IDT7130 Only)
High-speed access
◆
◆
◆
◆
◆
◆
◆
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55ns (max.)
– Military: 25/35/55/100ns (max.)
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
◆
Low-power operation
– IDT7130/IDT7140SA
— Active: 550mW (typ.)
— Standby: 5mW (typ.)
– IDT7130/IDT7140LA
— Active: 550mW (typ.)
— Standby: 1mW (typ.)
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MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
Functional Block Diagram
OER
OEL
CE
R/W
L
CE
R/W
R
L
R
,
I/O0L- I/O7L
I/O0R-I/O7R
(1,2)
I/O
Control
I/O
Control
(1,2)
BUSY
L
BUSYR
A
9L
0L
A
9R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
10
10
ARBITRATION
and
INTERRUPT
LOGIC
CE
L
L
CE
OE
R/W
R
R
OE
R
R/W
L
(2)
(2)
INT
R
INTL
2689 drw 01
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
1
Jul.12.21