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5962-86816012A PDF预览

5962-86816012A

更新时间: 2024-11-25 23:00:11
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路输出元件
页数 文件大小 规格书
20页 638K
描述
8BIT SHIFT REGISTERS WITH 3 STATE OUTPUT REGISTERS

5962-86816012A 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:LCC-20针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.32
Is Samacsys:N其他特性:PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT
计数方向:RIGHT系列:HC/UH
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.0078 A
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:34 ns传播延迟(tpd):300 ns
认证状态:Qualified施密特触发器:No
筛选级别:MIL-STD-883座面最大高度:2.03 mm
子类别:Shift Register最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.89 mm最小 fmax:25 MHz
Base Number Matches:1

5962-86816012A 数据手册

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SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004  
SN54HC595 . . . J OR W PACKAGE  
SN74HC595 . . . D, DB, DW, N, OR NS PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
8-Bit Serial-In, Parallel-Out Shift  
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Can Drive Up  
To 15 LSTTL Loads  
Q
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
B
Q
C
D
A
Low Power Consumption, 80-µA Max I  
Typical t = 13 ns  
pd  
6-mA Output Drive at 5 V  
CC  
Q
SER  
OE  
Q
E
Q
12 RCLK  
F
Low Input Current of 1 µA Max  
Shift Register Has Direct Clear  
11  
10  
9
Q
SRCLK  
SRCLR  
G
Q
H
GND  
Q
H  
description/ordering information  
SN54HC595 . . . FK PACKAGE  
(TOP VIEW)  
The ’HC595 devices contain an 8-bit serial-in,  
parallel-out shift register that feeds an 8-bit D-type  
storage register. The storage register has parallel  
3-state outputs. Separate clocks are provided for  
both the shift and storage register. The shift  
register has a direct overriding clear (SRCLR)  
input, serial (SER) input, and serial outputs for  
cascading. When the output-enable (OE) input is  
high, the outputs are in the high-impedance state.  
3
2
1
20 19  
18  
SER  
OE  
Q
4
5
6
7
8
D
Q
17  
16  
E
NC  
NC  
15 RCLK  
14  
9 10 11 12 13  
Q
F
SRCLK  
Q
G
Both the shift register clock (SRCLK) and storage  
register clock (RCLK) are positive-edge triggered.  
If both clocks are connected together, the shift  
register always is one clock pulse ahead of the  
storage register.  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Tube of 40  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC595N  
SN74HC595N  
SN74HC595D  
SN74HC595DR  
SN74HC595DT  
SN74HC595DW  
SN74HC595DWR  
SN74HC595NSR  
SN74HC595DBR  
SNJ54HC595J  
SNJ54HC595W  
SNJ54HC595FK  
HC595  
−40°C to 85°C  
SOIC − DW  
HC595  
SOP − NS  
SSOP − DB  
CDIP − J  
HC595  
HC595  
SNJ54HC595J  
SNJ54HC595W  
SNJ54HC595FK  
−55°C to 125°C  
CFP − W  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢕ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢌ ꢰꢊ ꢗꢏ ꢎ ꢊꢓꢉꢂ ꢓꢂꢇ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢕ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢇ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

5962-86816012A 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54HC595FK TI

完全替代

8BIT SHIFT REGISTERS WITH 3 STATE OUTPUT REGISTERS

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