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5962-8416201VDA PDF预览

5962-8416201VDA

更新时间： 2024-01-02 13:40:12
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
20页 593K
描述
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

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5962-8416201VDA 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82Is Samacsys：N
计数方向：RIGHT系列：HC/UH
JESD-30 代码：R-CDFP-F14JESD-609代码：e0
逻辑集成电路类型：SERIAL IN PARALLEL OUT位数：8
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：265 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class V
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：FLAT
端子位置：DUAL触发器类型：POSITIVE EDGE
Base Number Matches：1

5962-8416201VDA 数据手册

 浏览型号5962-8416201VDA的Datasheet PDF文件第2页浏览型号5962-8416201VDA的Datasheet PDF文件第3页浏览型号5962-8416201VDA的Datasheet PDF文件第4页浏览型号5962-8416201VDA的Datasheet PDF文件第5页浏览型号5962-8416201VDA的Datasheet PDF文件第6页浏览型号5962-8416201VDA的Datasheet PDF文件第7页 
SN54HC164, SN74HC164  
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS  
SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003  
SN54HC164 . . . J OR W PACKAGE  
SN74HC164 . . . D, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Typical t = 20 ns  
pd  
4-mA Output Drive at 5 V  
A
B
V
CC  
Q
Q
Q
Q
H
G
F
Q
A
B
C
D
Low Input Current of 1 µA Max  
Q
Q
Q
AND-Gated (Enable/Disable) Serial Inputs  
Fully Buffered Clock and Serial Inputs  
Direct Clear  
E
CLR  
CLK  
8
GND  
description/ordering information  
SN54HC164 . . . FK PACKAGE  
(TOP VIEW)  
These 8-bit shift registers feature AND-gated  
serial inputs and an asynchronous clear (CLR)  
input. The gated serial (A and B) inputs permit  
complete control over incoming data; a low at  
either input inhibits entry of the new data and  
resets the first flip-flop to the low level at the next  
clock (CLK) pulse. A high-level input enables the  
other input, which then determines the state of the  
first flip-flop. Data at the serial inputs can be  
changed while CLK is high or low, provided the  
minimum setup time requirements are met.  
Clockingoccurs on the low-to-high-leveltransition  
of CLK.  
3
2
1
20 19  
18  
Q
Q
4
5
6
7
8
G
A
NC  
NC  
17  
16  
Q
F
Q
B
NC  
15 NC  
14  
9 10 11 12 13  
Q
Q
C
E
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC164N  
SN74HC164N  
SN74HC164D  
SOIC – D  
SN74HC164DR  
SN74HC164DT  
SN74HC164NSR  
SN74HC164PW  
SN74HC164PWR  
SN74HC164PWT  
SNJ54HC164J  
SNJ54HC164W  
SNJ54HC164FK  
HC164  
–40°C to 85°C  
SOP – NS  
TSSOP – PW  
HC164  
HC164  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HC164J  
SNJ54HC164W  
SNJ54HC164FK  
–55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

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