EEPROM
AS58C1001
Austin Semiconductor, Inc.
128K x 8 EEPROM
EEPROM Memory
AVAILABLE AS MILITARY
PIN ASSIGNMENT
(Top View)
32-Pin CFP (F & SF)
SPECIFICATIONS
l SMD 5962-38267
l MIL-STD-883
1
2
3
4
5
6
7
8
RDY/BUSY\
A16
A14
A12
A7
32 Vcc
31 A15
30 RES\
29 WE\
28 A13
27 A8
FEATURES
l High speed: 150, 200, and 250ns
l Data Retention: 10 Years
l Low power dissipation, active current (20mW/MHz (TYP)),
standby current (100µW(MAX))
l Single +5V (+10%) power supply
l Data Polling and Ready/Busy Signals
l Erase/Write Endurance (10,000 cycles in a page mode)
l Software Data protection Algorithm
l Data Protection Circuitry during power on/off
l Hardware Data Protection with RES pin
l Automatic Programming:
A6
A5
A4
A3
A2
A1
A0
I/O 0
I/O 1
I/O 2
Vss
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 I/O 7
20 I/O 6
19 I/O 5
18 I/O 4
17 I/O 3
9
10
11
12
13
14
15
16
32-Pin LCC (ECA)
Automatic Page Write: 10ms (MAX)
128 Byte page size
OPTIONS
l Timing
MARKINGS
4
3 2 1 31 32 30
150ns access
200ns access
250ns access
-15
-20
-25
A7
A6
A5
A4
A3
5
6
7
8
9
29 WE\
28 A13
27 A8
26 A9
l Packages
25 A11
24 OE\
23 A10
22 CE\
21 I/O 7
Ceramic LCC
Ceramic Flat Pack
Radiation Shielded Ceramic FP*
l Operating Temperature Ranges
-Military (-55oC to +125oC)
-Industrial (-40oC to +85oC)
ECA No. 208
No. 306
A2 10
A1 11
F
A0 12
SF No. 305
I/O 0 13
XT
IT
14 15 16 17 18 19 20
*NOTE: Package lid is connected to ground (Vss).
This EEPROM provides several levels of data protection. Hard-
ware data protection is provided with the RES pin, in addition to noise
protection on the WE signal and write inhibit during power on and off.
Software data protection is implemented using JEDEC Optional Stan-
dard algorithm.
The AS58C1001 is designed for high reliability in the most de-
manding applications. Data retention is specified for 10 years and
erase/write endurance is guaranteed to a minimum of 10,000 cycles in
the Page Mode.
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS58C1001 is a 1 Megabit CMOS
Electrically Erasable Programmable Read Only Memory (EEPROM)
organized as 131, 072 x 8 bits. The AS58C1001 is capable or in
system electrical Byte and Page reprogrammability.
The AS58C1001 achieves high speed access, low power consump-
tion, and a high level of reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology and
CMOS process and circuitry technology.
This device has a 128-Byte Page Programming function to make its
erase and write operations faster. The AS58C1001 features Data
Polling and a Ready/Busy signal to indicate completion of erase and
programming operations.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS58C1001
Rev. 2.5 6/00
1