TLK2711-SP
www.ti.com .............................................................................................................................................................. SGLS307D–JULY 2006–REVISED JULY 2009
1.6-Gbps to 2.5-Gbps Class V Transceiver
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FEATURES
•
1.6- to 2.5-Gbps (Gigabits Per Second)
Serializer/Deserializer
•
On-Chip PLL Provides Clock Synthesis From
Low-Speed Reference
•
•
Hot-Plug Protection
•
•
•
•
Low Power: <500 mW
High-Performance 68-Pin Ceramic Quad Flat
Pack Package (HFG)
3-V Tolerance on Parallel Data Input Signals
16-Bit Parallel TTL-Compatible Data Interface
•
•
Low-Power Operation
Ideal for High-Speed Backplane Interconnect
and Point-to-Point Data Link
Programmable Preemphasis Levels on
Serial Output
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Military Temperature Range
•
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Interfaces to Backplane, Copper Cables, or
Optical Converters
(–55°C to 125°C Tcase)
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Loss of Signal (LOS) Detection
On-Chip 8-Bit/10-Bit Encoding/Decoding,
Comma Detect
Integrated 50-Ω Termination Resistors on RX
DESCRIPTION
The TLK2711 is a member of the WizardLink transceiver family of multigigabit transceivers, intended for use in
ultra-high-speed bidirectional point-to-point data transmission systems. The TLK2711 supports an effective serial
interface speed of 1.6 Gbps to 2.5 Gbps, providing up to 2 Gbps of data bandwidth.
The primary application of the TLK2711 is to provide high-speed I/O data channels for point-to-point baseband
data transmission over controlled impedance media of approximately 50 Ω. The transmission media can be
printed circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is
dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
This device can also be used to replace parallel data transmission architectures by providing a reduction in the
number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is
delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance
backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and
cost savings over parallel solutions, as well as scalability for higher data rates in the future.
The TLK2711 performs parallel-to-serial and serial-to-parallel data conversion. The clock extraction functions as
a physical layer (PHY) interface device. The serial transceiver interface operates at a maximum speed of 2.5
Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (TXCLK). The
16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting
20-bit word is then transmitted differentially at 20 times the reference clock (TXCLK) rate. The receiver section
performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data
to the recovered clock (RXCLK). It then decodes the 20-bit wide data using the 8-bit/10-bit decoding format
resulting in 16 bits of parallel data at the receive data terminals (RXD0–RXD15). The outcome is an effective
data payload of 1.28 Gbps to 2 Gbps (16 bits data × the frequency).
The TLK2711 is available in a 68-pin ceramic nonconductive tie-bar package (HFG).
NOTE:
The errata noted in the commercial TLK2711 device titled "Errata to the TLK2711,
1.6-to-2.7 GBPS Transceiver Data Sheet– PLL False Lock Problem" does not apply to
the TLK2711-SP device. The TLK2711-SP is functionally equivalent to the TLK2711A
commercial device.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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