Datasheet > 5962-01533

5962-01533

更新时间： 2022-11-26 01:28:37

品牌	Logo	应用领域
艾法斯 - AEROFLEX		静态存储器
页数	文件大小	规格书
14页	138K
描述
16Megabit SRAM MCM

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5962-01533 数据手册

Standard Products

QCOTS^TMUT8Q512K32 16Megabit SRAM MCM

Data Sheet

June, 2003

FEATURES

INTRODUCTION

The QCOTS^TMUT8Q512K32 Quantified Commercial

Off-the-Shelf product is a high-performance 2M byte

(16Mbit) CMOS static RAM multi-chip module (MCM),

organized as four individual 524,288 x 8 bit SRAMs with a

common output enable. Memory expansion is provided by

an active LOW chip enable (En), an active LOW output

enable (G), and three-state drivers. This device has a power-

down feature that reduces power consumption by more than

90% when deselected.

25ns maximum (3.3 volt supply) address access time

MCM contains four (4) 512K x 8 industry-standard

asynchronous SRAMs; the control architecture allows

operation as 8, 16, 24, or 32-bit data width

TTL compatible inputs and output levels, three-state

bidirectional data bus

Typical radiation performance

- Total dose: 50krads

- SEL Immune >80 MeV-cm²/mg

- LET_TH(0.25) = >10 MeV-cm²/mg

- Saturated Cross Section cm²per bit, 5.0E-9

- <1E-8 errors/bit-day, Adams 90% geosynchronous

heavy ion

Writing to each memory is accomplished by taking the chip

enable (En) input LOW and write enable ( Wn) inputs LOW.

Data on the I/O pins is then written into the location

specified on the address pins (A₀through A₁₈). Reading

Packaging options:

from the device is accomplished by taking the chip enable

(En) and output enable (G) LOW while forcing write enable

(Wn) HIGH. Under these conditions, the contents of the

memory location specified by the address pins will appear

on the I/O pins.

- 68-lead dual cavity ceramic quad flatpack (CQFP) -

(weight 7.37 grams)

Standard Microcircuit Drawing5962-01533

- QML T and Q compliant part

The input/output pins are placed in a high impedance state

when the device is deselected (En HIGH), the outputs are

disabled (G HIGH), or during a write operation (En LOW

and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by

making Wn along with En a common input to any

combination of the discrete memory die.

W₃

W₂

W₁

W₀

E₂

E₃

E₀

E₁

A(18:0)

512K x 8

DQ(31:24)

DQ(23:16)

DQ(15:3)

DQ(7:0)

DQ3(7:0)

DQ2(7:0)

DQ1(7:0)

DQ0(7:0)

Figure 1. UT8Q512K32 SRAM Block Diagram

12 3 4 5 6 7...14

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