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595KB525M000DGR PDF预览

595KB525M000DGR

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
12页 89K
描述
Oscillator

595KB525M000DGR 数据手册

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Si595  
REVISION D  
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)  
10 TO 525 MHZ  
Features  
Available with any-rate output  
frequencies from 10 to 525 MHz  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
®
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
Pb-free/RoHS-compliant  
–40 to +85 ºC operating range  
3rd generation DSPLL with  
superior jitter performance  
Internal fixed fundamental mode  
crystal frequency ensures high  
reliability and low aging  
Applications  
Ordering Information:  
See page 7.  
SONET/SDH (OC-3/12/48)  
Networking  
SD/HD SDI/3G SDI video  
FTTx  
Clock recovery and jitter cleanup PLLs  
FPGA/ASIC clock generation  
Pin Assignments:  
Description  
See page 6.  
®
The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to  
provide a low-jitter clock at high frequencies. The Si595 is available with  
any-rate output frequency from 10 to 525 MHz. Unlike traditional VCXOs,  
where a different crystal is required for each output frequency, the Si595  
uses one fixed crystal to provide a wide range of output frequencies. This IC-  
based approach allows the crystal resonator to provide exceptional  
frequency stability and reliability. In addition, DSPLL clock synthesis  
provides supply noise rejection, simplifying the task of generating low-jitter  
clocks in noisy environments. The Si595 IC-based VCXO is factory-  
configurable for a wide variety of user specifications including frequency,  
supply voltage, output format, tuning slope, and absolute pull range (APR).  
Specific configurations are factory programmed at time of shipment, thereby  
eliminating the long lead times associated with custom oscillators.  
(Top View)  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
GND  
Functional Block Diagram  
CLK– CLK+  
VDD  
Any-rate  
10–525 MHz  
DSPLL®  
Fixed  
Frequency  
XO  
Clock Synthesis  
ADC  
Vc  
OE  
GND  
Preliminary Rev. 0.2 8/09  
Copyright © 2009 by Silicon Laboratories  
Si595  

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