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590AC500M000DG PDF预览

590AC500M000DG

更新时间: 2024-11-05 21:09:03
品牌 Logo 应用领域
芯科 - SILICON 机械输出元件振荡器
页数 文件大小 规格书
15页 392K
描述
LVPECL Output Clock Oscillator,

590AC500M000DG 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.68
其他特性:TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TAPE最长下降时间:0.35 ns
频率调整-机械:NO频率稳定性:20%
JESD-609代码:e4安装特点:SURFACE MOUNT
标称工作频率:500 MHz最高工作温度:85 °C
最低工作温度:-40 °C振荡器类型:LVPECL
输出负载:50 OHM物理尺寸:7.0mm x 5.0mm x 1.8mm
最长上升时间:0.35 ns最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES最大对称度:55/45 %
端子面层:Gold (Au) - with Nickel (Ni) barrierBase Number Matches:1

590AC500M000DG 数据手册

 浏览型号590AC500M000DG的Datasheet PDF文件第2页浏览型号590AC500M000DG的Datasheet PDF文件第3页浏览型号590AC500M000DG的Datasheet PDF文件第4页浏览型号590AC500M000DG的Datasheet PDF文件第5页浏览型号590AC500M000DG的Datasheet PDF文件第6页浏览型号590AC500M000DG的Datasheet PDF文件第7页 
Si590/591  
1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)  
(10 MHZ TO 810 MHZ)  
Features  
Available with any-frequency output  
frequencies from 10 to 810 MHz  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry Standard 5x7 and  
3.2x5 mm packages  
Pb-free/RoHS-compliant  
–40 to +85 ºC operating  
temperature range  
®
3rd generation DSPLL with superior  
jitter performance: 1 ps max jitter  
Better frequency stability than SAW-  
based oscillators  
Internal fundamental mode crystal  
ensures high reliability  
Ordering Information:  
Applications  
See page 7.  
SONET/SDH (OC-3/12/48)  
Networking  
SD/HD SDI/3G SDI video  
Test and measurement  
Storage  
FPGA/ASIC clock generation  
Pin Assignments:  
See page 6.  
Description  
®
(Top View)  
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry  
to provide a low jitter clock at high frequencies. The Si590/591 supports any  
frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique  
crystal is required for each output frequency, the Si590/591 uses one fixed  
crystal to provide a wide range of output frequencies. This IC based  
approach allows the crystal resonator to provide exceptional frequency  
stability and reliability. In addition, DSPLL clock synthesis provides superior  
supply noise rejection, simplifying the task of generating low jitter clocks in  
noisy environments typically found in communication systems. The  
Si590/591 IC based XO is factory configurable for a wide variety of user  
specifications including frequency, supply voltage, output format, and  
stability. Specific configurations are factory programmed at time of shipment,  
thereby eliminating long lead times associated with custom oscillators.  
VDD  
1
2
3
6
5
4
NC  
OE  
CLK–  
CLK+  
GND  
Si590 (LVDS/LVPECL/CML)  
VDD  
1
2
3
6
5
4
OE  
NC  
Functional Block Diagram  
NC  
VDD  
CLK– CLK+  
GND  
CLK  
Si590 (CMOS)  
17 k*  
Any-rate  
10–810 MHz  
DSPLL®  
Clock  
Synthesis  
Fixed  
Frequency  
XO  
VDD  
1
2
3
6
5
4
OE  
NC  
OE  
CLK–  
CLK+  
17 k*  
GND  
Si591 (LVDS/LVPECL/CML)  
*Note: Output Enable High/Low Options Available – See Ordering Information  
GND  
Rev. 1.1 12/17  
Copyright © 2017 by Silicon Laboratories  
Si590/591  

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