Datasheet > 590AC400M000DGR

590AC400M000DGR

更新时间： 2024-11-06 10:50:59

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
12页	115K
描述
Oscillator

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中文翻译

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数据手册

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590AC400M000DGR 数据手册

Si590/591

1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)

(10 MHZ TO 810 MHZ)

Features

Si5602



Available with any-frequency output

frequencies from 10 to 810 MHz



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

–40 to +85 ºC operating

temperature range



3rd generation DSPLL with superior

jitter performance: 1 ps max jitter

Better frequency stability than SAW-

based oscillators



Internal fundamental mode crystal

ensures high reliability

Ordering Information:

Applications

See page 7.



SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video



Test and measurement

Storage

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

Description

(Top View)

The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si590/591 supports any

frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique

crystal is required for each output frequency, the Si590/591 uses one fixed

crystal to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The

Si590/591 IC based XO is factory configurable for a wide variety of user

specifications including frequency, supply voltage, output format, and

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

V_DD

CLK–

CLK+

GND

Si590 (LVDS/LVPECL/CML)

V_DD

Functional Block Diagram

V_DD

CLK– CLK+

GND

CLK

Si590 (CMOS)

17 k*

Any-rate

10–810 MHz

DSPLL^®

Clock

Synthesis

Fixed

Frequency

V_DD

CLK–

CLK+

17 k*

GND

Si591 (LVDS/LVPECL/CML)

*Note: Output Enable High/Low Options Available – See Ordering Information

GND

Rev. 1.0 8/11

Si590/591

12 3 4 5 6 7...12

中文翻译

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