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570BAB001614DG PDF预览

570BAB001614DG

更新时间: 2024-11-07 19:36:03
品牌 Logo 应用领域
芯科 - SILICON 机械输出元件振荡器
页数 文件大小 规格书
36页 562K
描述
LVDS Output Clock Oscillator, 300MHz Nom,

570BAB001614DG 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:2.24
其他特性:TRI-STATE; ENABLE/DISABLE FUNCTION; DIFFERENTIAL OUTPUT; TAPE最长下降时间:0.35 ns
频率调整-机械:NO频率稳定性:50%
JESD-609代码:e4安装特点:SURFACE MOUNT
标称工作频率:300 MHz最高工作温度:85 °C
最低工作温度:-40 °C振荡器类型:LVDS
输出负载:100 OHM物理尺寸:7.0mm x 5.0mm x 1.8mm
最长上升时间:0.35 ns最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES最大对称度:55/45 %
端子面层:Gold (Au) - with Nickel (Ni) barrierBase Number Matches:1

570BAB001614DG 数据手册

 浏览型号570BAB001614DG的Datasheet PDF文件第2页浏览型号570BAB001614DG的Datasheet PDF文件第3页浏览型号570BAB001614DG的Datasheet PDF文件第4页浏览型号570BAB001614DG的Datasheet PDF文件第5页浏览型号570BAB001614DG的Datasheet PDF文件第6页浏览型号570BAB001614DG的Datasheet PDF文件第7页 
Si570/Si571  
10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO  
Features  
Any programmable output  
frequencies from 10 to 945 MHz and  
select frequencies to 1.4 GHz  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
2
Available LVPECL, CMOS,  
LVDS, and CML outputs  
Industry-standard 5x7 mm  
package  
Pb-free/RoHS-compliant  
1.8, 2.5, or 3.3 V supply  
I C serial interface  
®
3rd generation DSPLL with superior  
jitter performance  
3x better frequency stability than  
SAW-based oscillators  
Applications  
Ordering Information:  
SONET/SDH  
xDSL  
10 GbE LAN/WAN  
ATE  
High performance  
instrumentation  
Low-jitter clock generation  
Optical modules  
Clock and data recovery  
See page 31.  
Pin Assignments:  
See page 30.  
Description  
(Top View)  
®
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL  
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-  
programmable to any output frequency from 10 to 945 MHz and select frequencies  
SDA  
7
2
NC  
VDD  
1
2
3
6
5
4
to 1400 MHz with <1 ppb resolution. The device is programmed via an I C serial  
interface. Unlike traditional XO/VCXOs where a different crystal is required for  
each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL  
clock synthesis IC to provide any-frequency operation. This IC-based approach  
allows the crystal resonator to provide exceptional frequency stability and  
reliability. In addition, DSPLL clock synthesis provides superior supply noise  
rejection, simplifying the task of generating low-jitter clocks in noisy environments  
typically found in communication systems.  
OE  
CLK–  
CLK+  
GND  
8
SCL  
Functional Block Diagram  
Si570  
CLK- CLK+  
VDD  
SDA  
7
OE  
VC  
VDD  
1
2
3
6
5
4
10-1400 MHz  
DSPLLClock  
Synthesis  
Fixed  
Frequency  
XO  
SDA  
SCL  
OE  
CLK–  
CLK+  
Si571 only  
GND  
ADC  
8
SCL  
GND  
Si571  
VC  
Rev. 1.6 6/18  
Copyright © 2018 by Silicon Laboratories  
Si570/Si571  

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