Datasheet > 554HE1134M000G

554HE1134M000G

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
12页	217K
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Oscillator

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554HE1134M000G 数据手册

Si554

PRELIMINARY DATA SHEET

QUAD FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

Features

ꢀ

Available with any-rate output

frequencies from 10–945 MHz and

select frequencies to 1.4 GHz

ꢀ

Internal fixed crystal frequency

ensures high reliability and low

aging

Si5602

ꢀ

Four selectable output frequencies ꢀ Available CMOS, LVPECL, LVDS

& CML outputs

3rd generation DSPLL with superior

jitter performance

ꢀ

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

ꢀ

3x better frequency stability than

SAW-based oscillators

ꢀ

Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 8.

ꢀ

SONET/SDH

xDSL

10 GbE LAN / WAN

ꢀ

Low jitter clock generation

Optical Modules

Clock and data recovery

Pin Assignments:

See page 7.

Description

The Si554 quad frequency VCXO utilizes Silicon Laboratories advanced

DSPLL circuitry to provide a very low jitter clock for all output frequencies.

(Top View)

The Si554 is available with any-rate output frequency from 10 to 945 MHz

and select frequencies to 1400 MHz. Unlike traditional VCXOs where a

different crystal is required for each output frequency, the Si554 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments typically found in communication

systems. The Si554 IC-based VCXO is factory configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

FS[1]

V_C

V_DD

CLK–

CLK+

GND

FS[0]

Functional Block Diagram

V_DD

CLK- CLK+

Any-rate

10–1400 MHz

DSPLL^®

Fixed

Frequency XO

FS0

FS1

Clock Synthesis

ADC

V_c

GND

Preliminary Rev. 0.3 5/06

Si554

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

12 3 4 5 6 7...12

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