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54LS365AFMQB PDF预览

54LS365AFMQB

更新时间: 2024-02-29 23:08:37
品牌 Logo 应用领域
美国国家半导体 - NSC 逻辑集成电路输出元件驱动
页数 文件大小 规格书
6页 134K
描述
Hex TRI-STATE Buffers

54LS365AFMQB 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknown风险等级:5.35
其他特性:WITH DUAL OUTPUT ENABLE系列:LS
JESD-30 代码:S-CQCC-N20长度:8.89 mm
逻辑集成电路类型:BUS DRIVER位数:6
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):25 ns
认证状态:COMMERCIAL座面最大高度:1.905 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子面层:NOT SPECIFIED端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:8.89 mmBase Number Matches:1

54LS365AFMQB 数据手册

 浏览型号54LS365AFMQB的Datasheet PDF文件第2页浏览型号54LS365AFMQB的Datasheet PDF文件第3页浏览型号54LS365AFMQB的Datasheet PDF文件第4页浏览型号54LS365AFMQB的Datasheet PDF文件第5页浏览型号54LS365AFMQB的Datasheet PDF文件第6页 
June 1989  
54LS365A/DM54LS365A/DM74LS365A  
Hex TRI-STATE Buffers  
É
General Description  
This device contains six independent gates each of which  
performs a non-inverting buffer function. The outputs have  
the TRI-STATE feature. When enabled, the outputs exhibit  
the low impedance characteristics of a standard LS output  
with additional drive capability to permit the driving of bus  
lines without external resistors. When disabled, both the  
output transistors are turned off presenting a high-imped-  
ance state to the bus line. Thus the output will act neither as  
a significant load nor as a driver. To minimize the possibility  
that two outputs will attempt to take a common bus to oppo-  
site logic levels, the disable time is shorter than the enable  
time of the outputs.  
Features  
Y
Alternate Military/Aerospace device (54LS365A) is  
available. Contact a National Semiconductor Sales Of-  
fice/Distributor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6427–1  
Order Number 54LS365ADMQB, 54LS365AFMQB, 54LS365ALMQB,  
DM54LS365AJ, DM54LS365AW, DM74LS265AM or DM74LS365AN  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
Function Table  
e
Y
A
Input  
G2  
Output  
Y
G1  
A
H
X
L
X
H
L
X
X
H
L
Hi-Z  
Hi-Z  
H
L
L
L
e
e
e
H
L
High Logic Level  
Low Logic Level  
X
Either Low or High Logic Level  
e
Hi-Z  
TRI-STATE (Outputs are disabled)  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6427  
RRD-B30M105/Printed in U. S. A.  

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