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54LS160ADMQB PDF预览

54LS160ADMQB

更新时间: 2024-09-21 22:39:03
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器逻辑集成电路
页数 文件大小 规格书
9页 176K
描述
Synchronous Presettable BCD Decade Counters

54LS160ADMQB 数据手册

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May 1992  
54LS160A/DM74LS160A, 54LS162A/DM74LS162A  
Synchronous Presettable BCD Decade Counters  
General Description  
Features  
Y
Synchronous counting and loading  
The ’LS160 and ’LS162 are high speed synchronous dec-  
ade counters operating in the BCD (8421) sequence. They  
are synchronously presettable for application in programma-  
ble dividers and have two types of Count Enable inputs plus  
a Terminal Count output for versatility in forming synchro-  
nous multistage counters. The ’LS160 has an asynchronous  
Master Reset input that overrides all other inputs and forces  
the outputs LOW. The ’LS162 has a Synchronous Reset  
input that overrides counting and parallel loading and allows  
all outputs to be simultaneously reset on the rising edge of  
the clock.  
Y
High speed synchronous expansion  
Y
Typical count rate of 35 MHz  
Y
Fully edge triggered  
Connection Diagram  
Dual-In-Line Package  
TL/F/10177–1  
*MR for ’LS160  
*SR for ’LS162  
Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB,  
54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM,  
DM74LS160AN, DM74LS162AM or DM74LS162AN  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
Logic Symbol  
Pin  
Description  
Names  
CEP  
Count Enable Parallel Input  
CET  
Count Enable Trickle Input  
Clock Pulse Input (Active Rising Edge)  
Asynchronous Master Reset  
Input (Active LOW)  
CP  
MR (’160)  
SR (’162)  
Synchronous Reset  
Input (Active LOW)  
P0P3  
PE  
Parallel Data Inputs  
Parallel Enable Input  
(Active LOW)  
Q0Q3  
TC  
Flip-Flop Outputs  
TL/F/10177–2  
e
e
V
Pin 16 *MR for ’LS160  
Pin 8 *SR for ’LS162  
Terminal Count Output  
CC  
GND  
C
1995 National Semiconductor Corporation  
TL/F/10177  
RRD-B30M105/Printed in U. S. A.  

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