5秒后页面跳转
54HSC PDF预览

54HSC

更新时间: 2024-09-23 22:16:07
品牌 Logo 应用领域
DYNEX /
页数 文件大小 规格书
10页 95K
描述
Radiation hard 16-Bit ParallelError Detection & Correction

54HSC 数据手册

 浏览型号54HSC的Datasheet PDF文件第2页浏览型号54HSC的Datasheet PDF文件第3页浏览型号54HSC的Datasheet PDF文件第4页浏览型号54HSC的Datasheet PDF文件第5页浏览型号54HSC的Datasheet PDF文件第6页浏览型号54HSC的Datasheet PDF文件第7页 
54HSC/T630  
Radiation hard 16-Bit ParallelError  
Detection & Correction  
Replaces June 1999 version, DS3595-4.0  
DS3595-5.0 January 2000  
The 54HSC/T630 is a 16-bit parallel Error Detection and  
Correction circuit. It uses a modified Hamming code to  
generate a 6-bit check word from each 16-bit data word. The  
check word is stored with the data word during a memory write  
cycle. During a memory read cycle a 22-bit word is taken from  
memory and checked for errors.  
Single bit errors in data words are flagged and corrected.  
Single bit errors in check words are flagged but not corrected.  
The position of the incorrect bit is pinpointed, in both cases, by  
the 6-bit error syndrome code which is output during the error  
correction cycle.  
Two bit errors are flagged but not corrected. Any  
combination of two bit errors occurring within the 22-bit word  
read from memory, (ie two errors in the 16-bit data word, two  
bits in the 16-bit check word or one error in each) will be  
correctly identified.  
The gross errors of all bits, low or high, will be detected.  
The control signals S1 and S0 select the function to be  
performed by the EDAC They control the generation of check  
words and the latching and correction of data (see table 1)  
When errors are detected, flags are placed on outputs SEF  
and DEF (see table 2).  
Figure 1: Block Diagram  
FEATURES  
Radiation Hard:  
Dose Rate Upset Exceeding 3x1010 Rad(Si)/sec  
Total Dose for Functionality Upto 1x106 Rad(Si)  
High SEU Immunity, Latch Up Free  
CMOS-SOS Technology  
All Inputs and Outputs Fully TTL Compatible (54HST630)  
or CMOS Compatible (54HSC630)  
Low Power  
Detects and Corrects Single-Bit Errors  
Detects and Flags Dual-Bit Errors  
High Speed:  
Write Cycle - Generates Checkword In 40ns Typical  
Read Cycle - Flags Errors In 20ns Typical  
1/10  

与54HSC相关器件

型号 品牌 获取价格 描述 数据表
54HSC/TSERIES ETC

获取价格

Radiation Hard High Speed CMOS/SOS Logic
54HSC00CB ETC

获取价格

Quad 2-input NAND Gate
54HSC00CS ETC

获取价格

Quad 2-input NAND Gate
54HSC00FB ETC

获取价格

Quad 2-input NAND Gate
54HSC00FE DYNEX

获取价格

NAND Gate, HSC Series, 4-Func, 2-Input, CMOS, CDFP14
54HSC00FL DYNEX

获取价格

NAND Gate, HSC Series, 4-Func, 2-Input, CMOS, CDFP14
54HSC00FS ETC

获取价格

Quad 2-input NAND Gate
54HSC00LB DYNEX

获取价格

NAND Gate, HSC Series, 4-Func, 2-Input, CMOS, CQCC20
54HSC02CB ETC

获取价格

Quad 2-input NOR Gate
54HSC02CS ETC

获取价格

Quad 2-input NOR Gate