Datasheet > 54HC08_V01

54HC08_V01

更新时间： 2022-02-26 13:47:43

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描述
High Speed CMOS Logic

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54HC08_V01 数据手册

High Speed CMOS Logic – 54HC08

Rev 1.0

07/02/19

Quad 2-Input AND Gate in bare die form

Description

Features:

The 54HC08 quad 2-input AND gate is fabricated using

a 2.5µm 5V CMOS process combining high speed

LSTTL performance with CMOS low power. The device

consists of four independent 2-input AND gates with

standard push-pull outputs and performs the Boolean

function Y = A ● B or Y = A + B. Device inputs are

compatible with standard CMOS outputs; with pull-up

resistors, they are compatible with LSTTL outputs. All

inputs are protected against ESD and excess voltage

transients.

Output Drive Capability: 10 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

Function compatible with 54LS08

High Noise Immunity CMOS process

Full Military Temperature Range.

Ordering Information

Die Dimensions in µm (mils)

The following part suffixes apply:

1200 (47)

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

1200 x 1350

Die Size (Unsawn)

µm

mils

47 x 53

Sawn Wafer on Tape – On request

85 x 85

Minimum Bond Pad Size

3.35 x 3.35

µm

mils

Unsawn Wafer – On request

350 (±20)

Die Thickness

µm

mils

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

13.78 (±0.79)

Top Metal Composition

Back Metal Composition

Al 1%Si 1.1µm

N/A – Bare Si

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