March 1993
54FCT/74FCT273
Octal D Flip-Flop
General Description
Features
Y
CC
I
reduced to 40.0 mA
The ’FCT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
Y
Y
Y
Y
Y
Y
Y
Y
Ideal buffer for MOS microprocessor or memory
Eight edge-triggered D flip-flops
Buffered common clock
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
Buffered, asynchronous master reset
TTL input and output level compatible
TTL levels accept CMOS levels
e
I
48 mA (Com), 32 mA (Mil)
OL
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
NSC 54/74FCT273 is pin and functionally equivalent to
IDT 54/74FCT273
Y
Military product compliant to MIL-STD-883 and
Ý
Standard Military Drawing 5962-87656
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
TL/F/10146–1
TL/F/10146–2
TL/F/10146–3
Pin Names
Description
Pin Assignment
for LCC
D –D
0
Data Inputs
7
MR
CP
Master Reset
Clock Pulse Input
Data Outputs
Q –Q
0
7
TL/F/10146–4
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10146
RRD-B30M105/Printed in U. S. A.