Datasheet > 54F74DC

54F74DC

更新时间： 2024-01-17 10:55:22

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路
页数	文件大小	规格书
6页	20K
描述
FLIP-FLOP\|DUAL\|D TYPE\|F-TTL\|DIP\|14PIN\|CERAMIC

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技术参数
数据手册

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54F74DC 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	14
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.27	系列：	F/FAST
JESD-30 代码：	R-CDIP-T14	逻辑集成电路类型：	D FLIP-FLOP
位数：	1	功能数量：	2
端子数量：	14	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出极性：	COMPLEMENTARY
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
传播延迟（tpd）：	10.5 ns	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	MILITARY
端子形式：	THROUGH-HOLE	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	最小 fmax：	125 MHz
Base Number Matches：	1

54F74DC 数据手册

MICROCIRCUIT DATA SHEET

Original Creation Date: 06/25/97

Last Update Date: 07/08/97

CN54F74-X REV 0A0

Last Major Revision Date: 06/25/97

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

General Description

The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary

(Q/Q) outputs. Information at the input is transferred to the outputs on the positive

edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse

and is not directly related to the transition time of the positive-going pulse. After the

Clock Pulse Input threshold voltage has been passed, the Data inputs is locked out and

information present will not be transferred to the outputs until the next rising edge of

the Clock Pulse input.

Asynchronous Inputs:

LOW Input to Sd sets Q to HIGH level

LOW Input to Cd sets Q to LOW level

Clear and Set are Independent of clock

Simultaneous LOW on Cd and Sd makes both Q and Q HIGH

Industry Part Number

NS Part Numbers

54F74

54F74DC

Prime Die

M074

Processing

Subgrp Description

Temp (^oC)

Static tests at

+25

+70

+25

+70

+25

+70

+25

+70

Static tests at

Dynamic tests at

Functional tests at

Switching tests at

Quality Conformance Inspection

12 3 4 5 6

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