ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢅ
ꢁ
ꢅ
ꢆ
ꢇ
ꢁ
ꢂ
ꢃ
ꢄ ꢅ ꢈꢉꢊ ꢋ ꢉꢌꢍ ꢋ ꢎꢂꢏꢍ ꢃꢐꢊ ꢑꢐꢎꢍ ꢂꢏꢒ ꢎꢐ ꢓ ꢊꢍ ꢋꢐ ꢎ
ꢄ
ꢅ
ꢅ
ꢁ
ꢅ
ꢍ
ꢍ
ꢔ
ꢊ
ꢋ
ꢕ
ꢖ
ꢈ
ꢍ
ꢋ
ꢂ
ꢋ
ꢐ
ꢗ
ꢌ
ꢋ
ꢘ
ꢌ
ꢋ
SCAS241A − MARCH 1990 − REVISED APRIL 1996
54AC16646 . . . WD PACKAGE
74AC16646 . . . DL PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebust Family
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
1DIR
1OE
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
1CLKAB
1SAB
GND
1A1
1CLKBA
1SBA
GND
1B1
Flow-Through Architecture Optimizes
PCB Layout
Distributed V
Minimize High-Speed Switching Noise
and GND Pin Configurations
CC
1A2
1B2
EPICt (Enhanced-Performance Implanted
V
V
CC
CC
CMOS) 1-mm Process
1A3
1A4
49 1B3
48 1B4
47 1B5
46 GND
45 1B6
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
500-mA Typical Latch-Up Immunity at
125°C
1A5 10
GND 11
1A6 12
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16646 are 16-bit bus transceivers that
consist of D-type flip-flops and control circuitry,
with 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The devices
can be used as two 8-bit transceivers or one 16-bit
transceiver. Data on the A or B bus is clocked into
the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the bus transceivers and
registers.
21
22
23
36
35
34
2A6
2B6
V
V
CC
CC
2A7
2B7
2A8 24
33 2B8
25
26
27
28
32
31
30
29
GND
2SAB
2CLKAB
2DIR
GND
2SBA
2CLKBA
2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. DIR determines which bus receives data when OE is active (low). In the isolation
mode (OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74AC16646 is packaged in the TI shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54AC16646 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC16646 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
ꢌ ꢏ ꢙꢐꢍꢍ ꢗ ꢋꢕ ꢐꢎꢔ ꢊꢍ ꢐ ꢏ ꢗꢋꢐꢒ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢘꢎ ꢗ ꢒ ꢌ ꢃꢋ ꢊꢗ ꢏ
ꢫ
ꢒ
ꢂ
ꢋ
ꢂ
ꢜ
ꢤ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢡ
ꢧ
ꢧ
ꢣ
ꢤ
ꢚ
ꢥ
ꢝ
ꢟ
ꢦ
ꢨ
ꢡ
ꢩ
ꢪ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢞ
ꢥ
ꢚ
ꢣ
ꢘ
ꢧ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢝ
ꢠ
ꢟ
ꢤ
ꢦ
ꢟ
ꢧ
ꢢ
ꢚ
ꢟ
ꢝ
ꢨ
ꢣ
ꢠ
ꢜ
ꢦ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢨ
ꢣ
ꢧ
ꢚ
ꢛ
ꢣ
ꢚ
ꢣ
ꢧ
ꢢ
ꢝ
ꢟ
ꢦ
ꢋꢣꢬ
ꢥ
ꢝ
ꢊ
ꢤ
ꢝ
ꢚꢧ
ꢡꢢ
ꢣ
ꢤ
ꢚ
ꢝ
ꢝ
ꢚ
ꢥꢤ
ꢞ
ꢥ
ꢧ
ꢞ
ꢭ
ꢥꢧ
ꢧ
ꢥ
ꢤꢚ
ꢮꢫ
ꢘ
ꢧ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢜ
ꢨꢥ ꢧ ꢥ ꢢ ꢣ ꢚ ꢣ ꢧ ꢝ ꢫ
ꢟ
ꢤ
ꢨ
ꢧ
ꢟ
ꢠ
ꢣ
ꢝ
ꢝ
ꢜꢤ
ꢯ
ꢞ
ꢟ
ꢣ
ꢝ
ꢤꢟ
ꢚ
ꢤ
ꢣ
ꢠꢣ
ꢝ
ꢝ
ꢥꢧ
ꢜꢪ
ꢮ
ꢜ
ꢤ
ꢠ
ꢪꢡ
ꢞ
ꢣ
ꢚ
ꢣ
ꢝ
ꢚ
ꢜ
ꢤ
ꢯ
ꢟ
ꢦ
ꢥ
ꢪ
ꢪ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443