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541FAB001022BAGR PDF预览

541FAB001022BAGR

更新时间: 2024-02-05 16:52:34
品牌 Logo 应用领域
芯科 - SILICON 振荡器
页数 文件大小 规格书
16页 621K
描述
CMOS Output Clock Oscillator,

541FAB001022BAGR 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.83
JESD-609代码:e4振荡器类型:CMOS
端子面层:Gold (Au) - with Nickel (Ni) barrier

541FAB001022BAGR 数据手册

 浏览型号541FAB001022BAGR的Datasheet PDF文件第2页浏览型号541FAB001022BAGR的Datasheet PDF文件第3页浏览型号541FAB001022BAGR的Datasheet PDF文件第4页浏览型号541FAB001022BAGR的Datasheet PDF文件第5页浏览型号541FAB001022BAGR的Datasheet PDF文件第6页浏览型号541FAB001022BAGR的Datasheet PDF文件第7页 
Ultra Series Crystal Oscillator  
Si541 Data Sheet  
Ultra Low Jitter Dual Any-Frequency XO (125 fs), 0.2 to 1500 MHz  
The Si541 Ultra Seriesoscillator utilizes Silicon Laboratories’ advanced 4th gen-  
eration DSPLL® technology to provide an ultra-low jitter, low phase noise clock at  
two selectable frequencies. The device is factory-programmed to provide any two  
selectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and maintains  
exceptionally low jitter for both integer and fractional frequencies across its operat-  
ing range. The Si541 offers excellent reliability and frequency stability as well as  
guaranteed aging performance. On-chip power supply filtering provides industry-  
leading power supply noise rejection, simplifying the task of generating low jitter  
clocks in noisy systems that use switched-mode power supplies. Offered in indus-  
try-standard 3.2x5 mm and 5x7 mm footprints, the Si541 has a dramatically simpli-  
fied supply chain that enables Silicon Labs to ship custom frequency samples 1-2  
weeks after receipt of order. Unlike a traditional XO, where a different crystal is re-  
quired for each output frequency, the Si541 uses one simple crystal and a DSPLL  
IC-based approach to provide the desired output frequencies. This process also  
guarantees 100% electrical testing of every device. The Si541 is factory-configura-  
ble for a wide variety of user specifications, including frequency, output format,  
and OE pin location/polarity. Specific configurations are factory-programmed at  
time of shipment, eliminating the long lead times associated with custom oscilla-  
tors.  
KEY FEATURES  
• Available with any two selectable frequencies  
from 0.2 MHz to 1500 MHz  
• Very low jitter: 125 fs Typ RMS  
(12 kHz – 20 MHz)  
• Excellent PSRR and supply noise immunity:  
–80 dBc Typ  
• 7 ppm stability option (-40 to 85 C)  
• 3.3 V, 2.5 V and 1.8 V V supply operation  
DD  
from the same part number  
• LVPECL, LVDS, CML, HCSL, CMOS, and  
Dual CMOS output options  
• 3.2×5, 5x7 mm package footprints  
• Any custom frequency available with 1-2  
week lead times  
APPLICATIONS  
Pin Assignments  
• 100G/200G/400G OTN, coherent optics  
• 10G/40G/100G optical ethernet  
1
2
3
6
5
4
VDD  
CLK-  
CLK+  
OE/FS  
FS/OE  
GND  
• 3G-SDI/12G-SDI/24G-SDI broadcast video  
• Servers, switches, storage, NICs, search  
acceleration  
• Test and measurement  
• Clock and data recovery  
• FPGA/ASIC clocking  
(Top View)  
Fixed  
Frequency  
Crystal  
Frequency  
Flexible  
DSPLL  
Pin #  
Descriptions  
Low  
Noise  
Driver  
1, 2  
Selectable via ordering option  
OE = Output enable; FS = Frequency Select  
DCO  
Digital  
Phase  
Detector  
Digital  
Phase Error  
Loop  
OSC  
Cancellation  
Filter  
3
4
5
GND = Ground  
Flexible  
Formats,  
1.8V – 3.3V  
Phase Error  
CLK+ = Clock output  
Fractional  
Operation  
Divider  
CLK- = Complementary clock output. Not used  
for CMOS.  
NVM  
Control  
Power Supply Regulation  
6
VDD = Power supply  
OE, Frequency Select  
(Pin Control)  
Built-in Power Supply  
Noise Rejection  
silabs.com | Building a more connected world.  
Rev. 1.0  

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