Datasheet > 532MB970M000G

532MB970M000G

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
12页	204K
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Oscillator

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532MB970M000G 数据手册

Si532

DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)

(10 MHZ TO 1.4 GHZ)

Features

Si5602

ꢀ

Available with any-rate output

ꢀ

Internal fixed crystal frequency

ensures high reliability and low

aging

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

ꢀ

Two selectable output frequencies ꢀ Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

3rd generation DSPLL with superior

ꢀ

jitter performance

ꢀ

3x better frequency stability than

SAW-based oscillators

ꢀ

Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 7.

ꢀ

SONET/SDH

Networking

SD/HD video

ꢀ

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

Description

(Top View)

The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced

DSPLL circuitry to provide a low jitter clock at high frequencies. The Si532 is

V_DD

available with any-rate output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is

required for each output frequency, the Si532 uses one fixed crystal

frequency to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The Si532 IC

based XO is factory configurable for a wide variety of user specifications

including frequency, supply voltage, output format, and temperature stability.

Specific configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

CLK–

CLK+

GND

(LVDS/LVPECL/CML)

V_DD

Functional Block Diagram

GND

CLK

V_DD

CLK– CLK+

(CMOS)

Any-rate

10–1400 MHz

DSPLL^®

Fixed

Frequency

Clock

Synthesis

GND

Rev. 1.0 7/06

Si532

12 3 4 5 6 7...12

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