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4DB0232KD PDF预览

4DB0232KD

更新时间: 2024-10-03 14:58:15
品牌 Logo 应用领域
瑞萨 - RENESAS 双倍数据速率
页数 文件大小 规格书
2页 774K
描述
Data Buffer for DDR4 Memory Modules

4DB0232KD 数据手册

 浏览型号4DB0232KD的Datasheet PDF文件第2页 
DDR4 Data Buffer 3200 Power  
Efficiency Model  
4DB0232KD1  
Short-Form Datasheet  
The 4DB0232KD1 also has a control bus interface that is used to  
synchronously receive control commands from Renesas’ DDR4  
Register at data rate speeds (e.g., in LRDIMM applications). This  
interface is commonly referred to as the BCOM bus. It consists of  
a 4-bit control bus BCOM[3:0], two dedicated control signals  
BCKE and BODT, a voltage reference input, and a differential  
clock input BCK_t/BCK_n.  
Description  
The 4DB0232KD1 is a JEDEC compliant DDR4 Data Buffer with  
dual 4-bit bidirectional “DQ” data registers and “DQS” differential  
strobes. It is designed for 1.2 VDD operation in DDR4 LRDIMM  
applications. The DQ host interface side of each 4-bit bidirectional  
data register is connected to a memory controller while the MDQ  
interface side is connected to two x4 DRAMs.  
The 4DB0232KD1 supports dedicated pins for ZQ calibration and  
for parity error alerts.  
All DQ and MDQ inputs are pseudo-differential with an internal  
voltage reference. All DQ and MDQ output drivers use external  
VDD termination and are optimized to drive single or dual  
terminated traces in DDR4 LRDIMM and NVDIMM-P applications.  
The differential DQS and MDQS strobes are used to  
synchronously sample the DQ and MDQ 4-bit data at the receiving  
end and are regenerated and driven by the DDR4 Data Buffer  
alongside the DQ and MDQ outputs on the opposite side of the  
device.  
Features  
All DDR4 data rates from 1600MT/s to 3200MT/s  
DDR4DB02 JEDEC Specification r1.0 compliant  
Supports all JEDEC LRDIMM raw card types  
Lower power dissipation reduces dependency on heat sinks in  
standard server configurations  
3.0 7.5 mm body, 0.5 0.5 mm ball pitch, 14 5 grid,  
53-CVBGA, optimized for DDR4 LRDIMM PCB layout  
Guaranteed operation at commercial grade temperatures  
Block Diagram  
TS/SPD  
RCD  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
24 Bits  
Command Address  
SPD  
40 Bits Data  
32 Bits Data  
©2020 Renesas Electronics Corporation  
1
April 30, 2020  

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