48L256
256-Kbit SPI Serial EERAM
Serial SRAM Features
Package Types (not to scale)
• Unlimited Reads/Unlimited Writes:
- Standard serial SRAM protocol
- Symmetrical timing for reads and writes
• SRAM Array:
8-Lead SOIC
(Top View)
CS
SO
1
2
3
8
7
6
VCC
- 32,768 x 8 bit
HOLD
SCK
• High-Speed SPI Interface:
VCAP
- Up to 66 MHz
VSS
4
5
SI
- Schmitt Trigger inputs for noise suppression
• Low-Power CMOS Technology:
- Active current: 5 mA (maximum)
- Standby current: 300 μA (at 85°C maximum)
- Hibernate current: 3 μA (at 85°C maximum)
Pin Function Table
Name
Function
Chip Select Input
Serial Data Output
CS
Hidden EEPROM Backup Features
SO
• Cell-Based Nonvolatile Backup:
- Mirrors SRAM array cell-for-cell
VCAP
VSS
SI
External Capacitor
Ground
- Transfers all data to/from SRAM cells in
parallel (all cells at same time)
Serial Data Input
Serial Clock Input
Hold Input
• Invisible-to-User Data Transfers:
SCK
HOLD
VCC
- VCC level monitored inside device
- SRAM automatically saved on power disrupt
- SRAM automatically restored on VCC return
• 100,000 Backups Minimum (at 85°C)
• 100 Years Retention (at 55°C)
Supply Voltage
Other Features of the 48L256
• Operating Voltage Range: 2.7V-3.6V
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
• ESD Protection: >2,000V
Packages
• 8-Lead SOIC
2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 1