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3D7428S-2

更新时间： 2024-09-16 03:57:51
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
7页 474K
描述
MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE

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中文翻译

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3D7428S-2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.65Is Samacsys：N
系列：3D输入频率最大值（fmax）：11 MHz
JESD-30 代码：R-PDSO-G16长度：10.335 mm
逻辑集成电路类型：SILICON DELAY LINE功能数量：1
抽头/阶步数：255端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：5 mA可编程延迟线：YES
Prop。Delay @ Nom-Sup：520.5 ns认证状态：Not Qualified
座面最大高度：2.71 mm子类别：Delay Lines
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.51 mmBase Number Matches：1

3D7428S-2 数据手册

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3D7428  
MONOLITHIC 8-BIT  
PROGRAMMABLE DELAY LINE  
(SERIES 3D7428 – LOW NOISE)  
FEATURES  
PACKAGES  
IN  
1
2
3
4
8
7
6
5
VDD  
OUT  
SC  
•
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology  
TTL/CMOS compatible inputs and outputs  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
SO  
IN  
AE  
SO/P0  
P1  
P2  
P3  
P4  
GND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
OUT  
MD  
P7  
P6  
SC  
P5  
AE  
GND  
SI  
3D7428Z-xx SOIC  
IN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
OUT  
MD  
P7  
Leading- and trailing-edge accuracy  
Programmable via serial or parallel interface  
Increment range: 0.25 through 20.0ns  
Delay tolerance: 0.5% (See Table 1)  
Supply current: 3mA typical  
AE  
SO/P0  
P1  
P2  
P6  
P3  
SC  
P5  
P4  
SI  
GND  
SI  
3D7428-xx DIP  
3D7428S-xx SOL  
Temperature stability: ±1.5% max (-40C to 85C)  
Vdd stability: ±0.5% max (4.75V to 5.25V)  
For mechanical dimensions, click here.  
For package marking details, click here.  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D7428 device is a versatile 8-bit programmable monolithic delay  
line. The input (IN) is reproduced at the output (OUT) without inversion,  
shifted in time as per the user selection. Delay values, programmed  
either via the serial or parallel interface, can be varied over 255 equal  
steps according to the formula:  
IN  
Signal Input  
OUT Signal Output  
MD  
AE  
Mode Select  
Address Enable  
P0-P7 Parallel Data Input  
SC  
SI  
Serial Clock  
Ti,nom = Tinh + i * Tinc  
Serial Data Input  
Serial Data Output  
where i is the programmed address, Tinc is the delay increment (equal  
to the device dash number), and Tinh is the inherent (address zero)  
delay. The device features both rising- and falling-edge accuracy.  
SO  
VDD +5 Volts  
GND Ground  
The all-CMOS 3D7428 integrated circuit has been designed as a reliable, economic alternative to hybrid  
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount  
16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART  
DELAYS AND TOLERANCES  
INPUT RESTRICTIONS  
Inherent  
Delay  
Delay  
Rec’d Max Absolute Max Rec’d Min  
Absolute Min  
Pulse Width  
6.5 ns  
NUMBER  
Delay (ns) Range (ns)  
Step (ns)  
Frequency Frequency  
Pulse Width  
80.0 ns  
3D7428-0.25  
3D7428-0.5  
3D7428-1  
3D7428-1.5  
3D7428-2  
3D7428-2.5  
3D7428-4  
3D7428-5  
3D7428-7.5  
3D7428-10  
3D7428-15  
3D7428-20  
6.25 MHz  
3.12 MHz  
1.56 MHz  
1.04 MHz  
781 KHz  
625 KHz  
390 KHz  
312 KHz  
208 KHz  
156 KHz  
104 KHz  
78 KHz  
77 MHz  
10.5 ± 2.0  
10.5 ± 2.0  
10.5 ± 2.0  
10.5 ± 2.0  
10.5 ± 2.0  
10.5 ± 2.5  
13.0 ± 4.0  
15.0 ± 5.0  
63.75 ± 0.4  
127.5 ± 0.5  
255.0 ± 1.0  
382.5 ± 1.5  
510.0 ± 2.0  
637.5 ± 2.5  
1020 ± 3.2  
1275 ± 4.0  
0.25 ± 0.12  
0.50 ± 0.25  
1.00 ± 0.50  
1.50 ± 0.75  
2.00 ± 1.00  
2.50 ± 1.25  
4.00 ± 2.00  
5.00 ± 2.50  
7.50 ± 3.75  
10.0 ± 5.00  
15.0 ± 9.00  
20.0 ± 12.0  
45 MHz  
22 MHz  
15 MHz  
11 MHz  
9.0 MHz  
5.6 MHz  
4.5 MHz  
3.0 MHz  
2.2 MHz  
1.5 MHz  
1.1 MHz  
160.0 ns  
320.0 ns  
480.0 ns  
640.0 ns  
800.0 ns  
1280.0 ns  
1600.0 ns  
2400.0 ns  
3200.0 ns  
4800.0 ns  
6400.0 ns  
11.0 ns  
22.0 ns  
33.0 ns  
44.0 ns  
55.0 ns  
88.0 ns  
110.0 ns  
165.0 ns  
220.0 ns  
330.0 ns  
440.0 ns  
20.0 ± 7.5 1912.5 ± 6.0  
23.5 ± 10  
33.0 ± 15  
42.0 ± 20  
2550 ± 8.0  
3825 ± 12  
5100 ± 16  
NOTES: Any delay increment between 0.25 and 20 ns not shown is also available as standard.  
See application notes section for more details  
2004 Data Delay Devices  
Doc #03003  
5/8/2006  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  
1234567

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