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3D7324-25 PDF预览

3D7324-25

更新时间: 2024-02-05 22:42:33
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
4页 259K
描述
MONOLITHIC QUADRUPLE FIXED DELAY LINE

3D7324-25 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.65Is Samacsys:N
系列:7324输入频率最大值(fmax):13.3 MHz
JESD-30 代码:R-PDIP-T14长度:19.305 mm
逻辑集成电路类型:ACTIVE DELAY LINE功能数量:1
抽头/阶步数:4端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
可编程延迟线:NO认证状态:Not Qualified
座面最大高度:4.58 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总延迟标称(td):25 ns
宽度:7.62 mmBase Number Matches:1

3D7324-25 数据手册

 浏览型号3D7324-25的Datasheet PDF文件第2页浏览型号3D7324-25的Datasheet PDF文件第3页浏览型号3D7324-25的Datasheet PDF文件第4页 
3D7324  
MONOLITHIC QUADRUPLE  
FIXED DELAY LINE  
(SERIES 3D7324)  
FEATURES  
PACKAGES  
All-silicon, low-power CMOS technology  
TTL/CMOS compatible inputs and outputs  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
I1  
N/C  
I2  
I3  
I4  
VDD  
N/C  
O1  
N/C  
O2  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
I1  
N/C  
I2  
1
2
3
4
5
6
7
14  
VDD  
N/C  
O1  
13  
12  
11  
10  
9
Low ground bounce noise  
I3  
N/C  
O2  
Leading- and trailing-edge accuracy  
Delay range: 6 through 6000ns  
I4  
N/C  
GND  
O3  
N/C  
GND  
O3  
O4  
8
O4  
Delay tolerance: 2% or 1.0ns  
8
3D7324D-xx  
SOIC  
Temperature stability: ±3% typ (-40C to 85C)  
Vdd stability: ±1% typical (4.75V to 5.25V)  
Minimum input pulse width: 20% of total delay  
14-pin Gull-Wing available as drop-in  
replacement for hybrid delay lines  
3D7324-xx  
DIP  
(150 Mil)  
3D7324G-xx Gull-Wing  
For mechanical dimensions, click here.  
For package marking details, click here.  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
I1  
Delay Line 1 Input  
Delay Line 2 Input  
Delay Line 3 Input  
Delay Line 4 Input  
Delay Line 1 Output  
Delay Line 2 Output  
Delay Line 3 Output  
Delay Line 4 Output  
The 3D7324 Quadruple Delay Line product family consists of fixed-  
delay CMOS integrated circuits. Each package contains four matched,  
independent delay lines. Delay values can range from 6ns through  
6000ns. The input is reproduced at the output without inversion,  
shifted in time as per the user-specified dash number. The 3D7324 is  
TTL- and CMOS-compatible, capable of driving ten 74LS-type loads,  
and features both rising- and falling-edge accuracy.  
I2  
I3  
I4  
O1  
O2  
O3  
O4  
VDD +5 Volts  
GND Ground  
The all-CMOS 3D7324 integrated circuit has been designed as a  
reliable, economic alternative to hybrid TTL fixed delay lines. It is  
offered in a standard 14-pin auto-insertable DIP and a space saving  
surface mount 14-pin SOIC.  
N/C  
No Connection  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART NUMBER  
DELAY  
PER LINE  
(ns)  
INPUT RESTRICTIONS  
Max Operating Absolute Max Min Operating  
Pulse Width  
9.0 ns  
DIP-14  
3D7324  
-6  
DIP-14  
SOIC-14  
Absolute Min  
Oper. P.W.  
4.0 ns  
3D7324G 3D7324D  
Frequency  
55.5 MHz  
41.6 MHz  
33.3 MHz  
22.2 MHz  
16.7 MHz  
13.3 MHz  
11.1 MHz  
8.33 MHz  
6.67 MHz  
3.33 MHz  
1.67 MHz  
Oper. Freq.  
125.0 MHz  
111.0 MHz  
100.0 MHz  
100.0 MHz  
100.0 MHz  
83.3 MHz  
71.4 MHz  
62.5 MHz  
50.0 MHz  
25.0 MHz  
12.5 MHz  
0.67 MHz  
0.33 MHz  
0.05 MHz  
-6  
-8  
-6  
-8  
6 ± 1.0  
-8  
12.0 ns  
15.0 ns  
4.5 ns  
8 ± 1.0  
-10  
-10  
-10  
5.0 ns  
10 ± 1.0  
15 ± 1.0  
20 ± 1.0  
25 ± 1.0  
30 ± 1.0  
40 ± 1.0  
50 ± 1.0  
100 ± 2.0  
200 ± 4.0  
-500  
-15  
-15  
-15  
22.5 ns  
5.0 ns  
-20  
-20  
-20  
30.0 ns  
5.0 ns  
-25  
-25  
-25  
37.5 ns  
6.0 ns  
-30  
-30  
-30  
45.0 ns  
7.0 ns  
-40  
-40  
-40  
60.0 ns  
8.0 ns  
-50  
-50  
-50  
75.0 ns  
10.0 ns  
20.0 ns  
40.0 ns  
750.0 ns  
1500.0 ns  
9000.0 ns  
-100  
-200  
-500  
-1000  
-6000  
-100  
-200  
-500  
-1000  
-6000  
-100  
-200  
-500  
-1000  
-6000  
150.0 ns  
300.0 ns  
5.00 MHz  
2.50 MHz  
0.42 MHz  
500 ± 10.0  
1000 ± 20  
6000 ±120  
-1000  
-6000  
NOTES: Any delay between 10 and 6000 ns not shown is also available.  
2006 Data Delay Devices  
Doc #06016  
5/10/2006  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  

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