Datasheet > 逻辑 > 延迟线> 3D3424-300

3D3424-300

更新时间： 2024-11-25 03:57:47

品牌	Logo	应用领域
DATADELAY		延迟线逻辑集成电路光电二极管
页数	文件大小	规格书
6页	359K
描述
MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

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3D3424-300 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	14
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.64	系列：	3424
输入频率最大值（fmax）：	0.074 MHz	JESD-30 代码：	R-PDIP-T14
长度：	19.305 mm	逻辑集成电路类型：	ACTIVE DELAY LINE
功能数量：	1	抽头/阶步数：	4
端子数量：	14	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	可编程延迟线：	YES
认证状态：	Not Qualified	座面最大高度：	4.58 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
总延迟标称（td）：	4509 ns	宽度：	7.62 mm
Base Number Matches：	1

3D3424-300 数据手册

3D3424

MONOLITHIC QUAD 4-BIT

PROGRAMMABLE DELAY LINE

(SERIES 3D3424)

FEATURES

PACKAGES

•

Four indep’t programmable lines on a single chip

VDD

All-silicon CMOS technology

Low quiescent current (5mA typical)

Leading- and trailing-edge accuracy

VDD

Vapor phase, IR and wave solderable

Increment range: 1ns through 300ns

Delay tolerance: 3% or 2ns (see Table 1)

Line-to-line matching: 1% or 1ns typical

Temperature stability: ±1.5% typical (-40C to 85C)

Vdd stability: ±0.5% typical (3.0V to 3.6V)

Minimum input pulse width: 10% of total delay

GND

SOIC-14

DIP-14

3D3424D-xx

3D3424-xx

For mechanical dimensions, click here.

For package marking details, click here.

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The 3D3424 device is a small, versatile, quad 4-bit programmable

monolithic delay line. Delay values, programmed via the serial interface,

can be independently varied over 15 equal steps. The step size (in ns) is

determined by the device dash number. Each input is reproduced at the

corresponding output without inversion, shifted in time as per user

selection. For each line, the delay time is given by:

I1-I4

Signal Inputs

O1-O4 Signal Outputs

Address Latch In

Serial Clock In

Serial Data In

Serial Data Out

VDD 3.3V

TD_n= T0 + A_n* TI

GND Ground

where T0 is the inherent delay, A_nis the delay address of the n-th line

and TI is the delay increment (dash number). The desired addresses are

shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The

serial interface can also be used to enable/disable each delay line. The 3D3424 operates at 3.3 volts and

has a typical T0 of 9ns. The 3D3424 is CMOS-compatible, capable of sourcing or sinking 4mA loads, and

features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable

DIP and a space saving surface mount 14-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

DELAYS & TOLERANCES (NS)

INPUT RESTRICTIONS

Part

Delay

Step

Inherent

Total

Relative

Max Frequency

Min Pulse Width

Number

Delay

Tolerance

Recom’d Absolute Recom’d

Absolute

3D3424-1

3D3424-1.5

3D3424-2

3D3424-4

3D3424-5

3D3424-10

3D3424-15

3D3424-20

3D3424-40

3D3424-50

3D3424-100

3D3424-200

3D3424-300

3% or 0.50ns 13.8 MHz 166 MHz

3% or 0.50ns 10.5 MHz 111 MHz

36 ns

48 ns

3.0 ns

1.0 ± 0.50 9.0 ± 2.0

1.5 ± 0.75 9.0 ± 2.0

2.0 ± 1.00 9.0 ± 2.0

4.0 ± 2.00 9.0 ± 2.0

5.0 ± 2.50 9.0 ± 2.0

10 ± 2.50 9.0 ± 2.0

15 ± 3.75 9.0 ± 2.0

20 ± 5.00 9.0 ± 2.0

40 ± 10.0 9.0 ± 2.0

50 ± 10.0 9.0 ± 2.0

100 ± 12.5 9.0 ± 2.0

24.0 ± 2.0

31.5 ± 2.0

39.0 ± 2.0

69.0 ± 2.0

84.0 ± 2.5

159 ± 5.0

234 ± 7.5

309 ± 10

609 ± 20

759 ± 25

1509 ± 50

4.5 ns

3% or 0.75ns

3% or 1.25ns

3% or 1.88ns

3% or 2.50ns

3% or 5.00ns

3% or 6.25ns

3% or 12.5ns

3% or 25.0ns

3% or 37.5ns

8.5 MHz

4.8 MHz

4.0 MHz

2.1 MHz

1.4 MHz

1.0 MHz

550 KHz

440 KHz

220 KHz

110 KHz

74 KHz

83 MHz

41 MHz

33 MHz

22 MHz

16 MHz

8.3 MHz

6.6 MHz

3.3 MHz

1.6 MHz

1.1 MHz

59 ns

6.0 ns

104 ns

126 ns

239 ns

351 ns

464 ns

914 ns

1.2 us

2.3 us

4.5 us

6.8 us

12.0 ns

15.0 ns

22.5 ns

30.0 ns

60.0 ns

75.0 ns

150 ns

300 ns

450 ns

200 ± 20.0 9.0 ± 2.0 3009 ± 100

300 ± 30.0 9.0 ± 2.0 4509 ± 150

NOTE: Any increment between 1ns and 300ns not shown is also available as standard

See page 4 for details regarding input restrictions

2006 Data Delay Devices

Doc #06020

6/6/2006

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

12 3 4 5 6

中文翻译

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与3D3424-300相关器件

型号	品牌	获取价格	描述	数据表
3D3424-4	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424-40	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424-5	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424-50	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424D-1	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424D-1.5	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424D-10	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424D-100	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424D-15	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
3D3424D-2	DATADELAY	获取价格	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

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