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3D3418S-3 PDF预览

3D3418S-3

更新时间: 2024-11-28 08:32:35
品牌 Logo 应用领域
DATADELAY 光电二极管逻辑集成电路延迟线
页数 文件大小 规格书
7页 446K
描述
Silicon Delay Line, Programmable, 1-Func, 255-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16

3D3418S-3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:SOIC
包装说明:0.300 INCH, SOIC-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84输入频率最大值(fmax):0.52 MHz
JESD-30 代码:R-PDSO-G16长度:10.335 mm
逻辑集成电路类型:SILICON DELAY LINE功能数量:1
抽头/阶步数:255端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
可编程延迟线:YES认证状态:Not Qualified
座面最大高度:2.68 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总延迟标称(td):785 ns
宽度:7.51 mm

3D3418S-3 数据手册

 浏览型号3D3418S-3的Datasheet PDF文件第2页浏览型号3D3418S-3的Datasheet PDF文件第3页浏览型号3D3418S-3的Datasheet PDF文件第4页浏览型号3D3418S-3的Datasheet PDF文件第5页浏览型号3D3418S-3的Datasheet PDF文件第6页浏览型号3D3418S-3的Datasheet PDF文件第7页 
3D3418  
MONOLITHIC 8-BIT  
PROGRAMMABLE DELAY LINE  
(SERIES 3D3418 – LOW NOISE)  
FEATURES  
PACKAGES  
All-silicon, low-power 3.3V CMOS technology  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
1
2
3
4
5
6
7
8
IN  
AE  
SO/P0  
P1  
P2  
P3  
P4  
GND  
16  
15  
14  
13  
12  
11  
10  
9
VDD  
OUT  
MD  
P7  
P6  
SC  
P5  
SI  
Low ground bounce noise  
IN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
OUT  
MD  
P7  
AE  
Leading- and trailing-edge accuracy  
Increment range: 0.25 through 7.5ns  
Delay tolerance: 1% (See Table 1)  
Temperature stability: ±3% typical (0C-70C)  
Vdd stability: ±1% typical (3.0V-3.6V)  
Static Idd: 1.3ma typical  
SO/P0  
P1  
P2  
P3  
P6  
SC  
P5  
P4  
GND  
SI  
3D3418S SOL  
(300 Mil)  
3D3418 DIP  
3D3418G Gull Wing  
Minimum input pulse width: 10% of total  
delay  
Programmable via 3-wire serial or 8-bit parallel interface  
For mechanical dimensions, click here.  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
IN  
Signal Input  
The 3D3418 Programmable 8-Bit Silicon Delay Line product family  
consists of 8-bit, user-programmable CMOS silicon integrated  
circuits. Delay values, programmed either via the serial or parallel  
interface, can be varied over 255 equal steps ranging from 250ps  
to 7.5ns inclusively. Units have a typical inherent (address 0)  
delay of 20ns (See Table 1). The input is reproduced at the output  
without inversion, shifted in time as per user selection. The  
3D3418 is CMOS-compatible, and features both rising- and  
falling-edge accuracy.  
OUT Signal Output  
MD  
AE  
Mode Select  
Address Enable  
P0-P7 Parallel Data Input  
SC  
SI  
Serial Clock  
Serial Data Input  
Serial Data Output  
SO  
VDD +3.3 Volts  
GND Ground  
The all-CMOS 3D3418 integrated circuit has been designed as a  
reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard 16-pin  
auto-insertable DIP and a space saving surface mount 16-pin SOIC.  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART  
DELAYS AND TOLERANCES  
INPUT RESTRICTIONS  
Step 0  
Step 255  
Delay  
Max Operating  
6.25 MHz  
Absolute Max Min Operating  
Absolute Min  
Oper P.W.  
5.5 ns  
NUMBER  
Delay (ns) Delay (ns)  
19.5 ± 3.0 83.25 ± 4.0  
19.5 ± 3.0 147.0 ± 4.0  
19.5 ± 3.0 274.5 ± 5.0  
20.0 ± 3.5 530.0 ± 6.0  
20.0 ± 3.5 785.0 ± 8.0  
Increment (ns) Frequency  
Oper Freq  
P.W.  
3D3418-0.25  
3D3418-0.5  
3D3418-1  
3D3418-2  
3D3418-3  
3D3418-4  
3D3418-5  
3D3418-7.5  
90 MHz  
80.0 ns  
160.0 ns  
320.0 ns  
640.0 ns  
960.0 ns  
1280.0 ns  
1600.0 ns  
2400.0 ns  
0.25 ± 0.15  
0.50 ± 0.25  
1.00 ± 0.50  
2.00 ± 1.00  
3.00 ± 1.50  
4.00 ± 2.00  
5.00 ± 2.50  
7.50 ± 3.75  
3.15 MHz  
1.56 MHz  
0.78 MHz  
0.52 MHz  
0.39 MHz  
0.31 MHz  
0.21 MHz  
45 MHz  
22 MHz  
11 MHz  
7.5 MHz  
5.5 MHz  
4.4 MHz  
2.9 MHz  
11.0 ns  
22.0 ns  
44.0 ns  
66.0 ns  
88.0 ns  
20.0 ± 3.5  
20.0 ± 3.5  
20.5 ± 3.5  
1040 ± 9.0  
1295 ± 10  
1933 ± 15  
110.0 ns  
165.0 ns  
NOTES: Any delay increment between 0.25 and 7.5 ns not shown is also available.  
All delays referenced to input pin  
2002 Data Delay Devices  
Doc #02006  
10/28/02  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

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