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3D3225H-1 PDF预览

3D3225H-1

更新时间： 2024-10-01 03:03:55
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
4页 242K
描述
MONOLITHIC 5-TAP FIXED DELAY LINE

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中文翻译

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3D3225H-1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.62Is Samacsys：N
其他特性：INPUT TO FIRST TAP DELAY =7.5NS系列：3225
输入频率最大值（fmax）：166.7 MHzJESD-30 代码：R-PDSO-G8
长度：9.46 mm逻辑集成电路类型：SILICON DELAY LINE
功能数量：1抽头/阶步数：5
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED可编程延迟线：NO
认证状态：Not Qualified座面最大高度：4.59 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总延迟标称（td）：11.5 ns宽度：6.35 mm
Base Number Matches：1

3D3225H-1 数据手册

 浏览型号3D3225H-1的Datasheet PDF文件第2页浏览型号3D3225H-1的Datasheet PDF文件第3页浏览型号3D3225H-1的Datasheet PDF文件第4页 
3D3225  
MONOLITHIC 5-TAP  
FIXED DELAY LINE  
(SERIES 3D3225)  
FEATURES  
PACKAGES  
IN  
O2  
1
2
3
4
8
7
6
5
VDD  
•
•
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology  
TTL/CMOS compatible inputs and outputs  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
O1  
O3  
O5  
IN  
NC  
NC  
O2  
NC  
VDD  
NC  
O1  
NC  
O3  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
O4  
GND  
3D3225Z-xx SOIC-8  
3D3225M-xx DIP-8  
Low ground bounce noise  
3D3225H-xx Gull-Wing  
Leading- and trailing-edge accuracy  
Delay range: 0.75ns through 3500ns  
Delay tolerance: 2% or 0.5ns  
IN  
NC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
NC  
NC  
O1  
O4  
GND  
NC  
O5  
NC  
8
O2  
NC  
NC  
O3  
3D3225-xx  
DIP-14  
Temperature stability: ±2% typical (-40C to 85C)  
Vdd stability: ±1% typical (3.0V-3.6V)  
Minimum input pulse width: 30% of total delay  
8-pin Gull-Wing available as drop-in  
replacement for hybrid delay lines  
O4  
3D3225G-xx Gull-Wing  
3D3225K-xx Unused pins  
removed  
NC  
NC  
O5  
GND  
3D3225S-xx SOL-16  
For mechanical dimensions, click here.  
For package marking details, click here.  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D3225 5-Tap Delay Line product family consists of fixed-delay  
CMOS integrated circuits. Each package contains a single delay line,  
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap  
(incremental) delay values can range from 0.75ns through 700ns. The  
input is reproduced at the outputs without inversion, shifted in time as  
per the user-specified dash number. The 3D3225 is TTL- and CMOS-  
compatible, capable of driving ten 74LS-type loads, and features both  
rising- and falling-edge accuracy.  
IN  
Delay Line Input  
O1  
O2  
O3  
O4  
O5  
Tap 1 Output (20%)  
Tap 2 Output (40%)  
Tap 3 Output (60%)  
Tap 4 Output (80%)  
Tap 5 Output (100%)  
VDD +3.3 Volts  
GND Ground  
The all-CMOS 3D3225 integrated circuit has been designed as a reliable, economic alternative to hybrid  
TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and space saving surface mount  
8-pin SOIC and 16-pin SOL packages.  
TABLE 1: PART NUMBER SPECIFICATIONS  
DASH  
TOLERANCES  
TOTAL  
INPUT RESTRICTIONS  
NUMBER  
TAP-TAP  
DELAY (ns)  
0.75 ± 0.4  
1.0 ± 0.5  
1.5 ± 0.7  
2.0 ± 0.8  
2.5 ± 1.0  
4.0 ± 1.3  
5.0 ± 1.5  
10.0 ± 2.0  
20.0 ± 4.0  
50.0 ± 10  
100 ± 20  
200 ± 40  
700 ± 140  
Rec’d Max  
Frequency  
41.7 MHz  
37.0 MHz  
31.2 MHz  
25.0 MHz  
22.2 MHz  
8.33 MHz  
13.3 MHz  
6.67 MHz  
3.33 MHz  
1.33 MHz  
0.67 MHz  
0.33 MHz  
0.10 MHz  
Absolute Max  
Rec’d Min  
Pulse Width  
12.0 ns  
13.5 ns  
16.0 ns  
20.0 ns  
22.5 ns  
30.0 ns  
37.5 ns  
75.0 ns  
150 ns  
Absolute Min  
Pulse Width  
3.00 ns  
DELAY (ns)  
3.0 ± 0.5*  
4.0 ± 0.5*  
6.0 ± 0.5*  
8.0 ± 0.5*  
10.0 ± 0.5*  
16.0 ± 0.7*  
25.0 ± 1.0  
50.0 ± 1.0  
100.0 ± 2.0  
250.0 ± 5.0  
500.0 ± 10  
1000 ± 20  
3500 ± 70  
Frequency  
166.7 MHz  
166.7 MHz  
166.7 MHz  
166.7 MHz  
125.0 MHz  
133.3 MHz  
66.7 MHz  
33.3 MHz  
16.7 MHz  
6.67 MHz  
3.33 MHz  
1.67 MHz  
0.48 MHz  
-.75  
-1  
-1.5  
-2  
-2.5  
-4  
-5  
-10  
-20  
-50  
-100  
-200  
-700  
3.00 ns  
3.00 ns  
3.00 ns  
4.00 ns  
6.00 ns  
7.50 ns  
15.0 ns  
30.0 ns  
375 ns  
75.0 ns  
750 ns  
1500 ns  
5250 ns  
150 ns  
300 ns  
1050 ns  
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns ± 1.0ns  
NOTE: Any
 
dash number between .75 and 700 not shown is also available as standard.  
2005 Data Delay Devices  
Doc #05003  
5/8/2006  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  
1234

中文翻译

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