Datasheet > 3511

3511

更新时间： 2024-11-24 02:58:39

品牌	Logo	应用领域
友顺 - UTC		/
页数	文件大小	规格书
7页	55K
描述
CMOS IC

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3511 数据手册

UTC 3511

CMOS IC

PC POWER SUPPLY

SUPERVISORS

DESCRIPTION

The UTC 3511 provides protection circuits, power

good output (PGO), fault protection latch (FPL_N),

and protection detector function (PDON_N) control.

It can minimize external components of switching

power supply systems in personal computer.

The Over Voltage Detector (OVD) monitors 3.3V,

5V, 12V input voltage level. The Under Voltage

Detector (UVD) monitors 3.3V, 5V input voltage level.

When OVD or UVD detect the fault voltage level, the

FPL_N is latched HIGH and PGO goes LOW. The

latch can be reset by PDON_N going HIGH. There is

2.4ms delay time for PDON_N turning off FPL_N.

When OVD and UVD detect the right voltage level,

the power good output (PGO) will be issue.

SOP-8

DIP-8

FEATURES

* The Over Voltage Detector (OVD) monitors

3.3V, 5V, 12V input voltage level.

* The Under Voltage Detector (UVD) monitors 3.3V,

5V input voltage level.

* Both of the power good output (PGO) and the fault

protection latch (FPL_N) are Open Drain Output.

* 75 ms time delay for UVD.

* 300 ms time delay for PGO.

* 38 ms for PDON_N input signal De-bounce.

* 73 us for internal signal De-glitches.

* 2.4 ms time delay for PDON_N turn-off FPL_N.

PIN CONFIGURATION

PGI

PGO

GND

FPL_N

VDD

PDON_N

V33

UTC

UNISONIC TECHNOLOGIES CO., LTD. 1

QW-R502-015,B

12 3 4 5 6 7

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