MX29F002/002N T/B
2M-BIT [256K x 8] CMOS FLASH MEMORY
FEATURES
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262,144x 8 only
-Datapolling&Togglebitfordetectionofprogramand
erase cycle completion.
Fast access time: 55/70/90/120ns
Lowpowerconsumption
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Sectorprotection
- 30mA maximum active current(5MHz)
- 1uA typical standby current
- Hardware method to disable any combination of
sectors from program or erase operations
-Sectorprotect/unprotectfor5Vonlysystemor5V/12V
system
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Programming and erasing voltage 5V ± 10%
Commandregisterarchitecture
- Byte Programming (7us typical)
- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte
x1, and 64K-Byte x 3)
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100,000minimumerase/programcycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
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Auto Erase (chip & sector) and Auto Program
-Automaticallyeraseanycombinationofsectorsorthe
whole chip with Erase Suspend capability.
-Automaticallyprogramsandverifiesdataatspecified
address
- B = Bottom Boot Sector
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HardwareRESETpin(onlyfor29F002T/B)
- Resets internal state machine to read mode
Low VCC write inhibit is equal to or less than 3.2V
Package type:
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EraseSuspend/EraseResume
- Suspends an erase operation to read data from, or
programdatato,asectorthatisnotbeingerased,then
resumestheeraseoperation.
- 32-pin PDIP
-32-pinPLCC
- 32-pin TSOP (Type 1)
Status Reply
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20 years data retention
GENERAL DESCRIPTION
MXIC'sFlashtechnologyreliablystoresmemorycontents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F002T/B uses a 5.0V ± 10% VCC
supply to perform the High Reliability Erase and auto
Program/Erasealgorithms.
The MX29F002T/B is a 2-mega bit Flash memory organ-
ized as 256K bytes of 8 bits only. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29F002T/B is
packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is
designedtobereprogrammedanderasedin-systemorin-
standardEPROMprogrammers.
ThestandardMX29F002T/Boffersaccesstimeasfastas
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F002T/B has separate chip enable (CE) and output
enable(OE)controls.
Thehighestdegreeoflatch-upprotectionisachievedwith
MXIC'sproprietarynon-epiprocess. Latch-upprotectionis
proved for stresses up to 100 milliamps on address and
data pin from -1V to VCC + 1V.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F002T/B uses a command register to manage this
functionality. Thecommandregisterallowsfor100%TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
REV. 1.5, MAR. 28, 2005
P/N: PM0547
1
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